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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2006, zarlink semiconductor inc. all rights reserved. features ima ? up to 16 t1, e1, j1, dsl links & up to 8 ima groups with 1 to 16 links/ima group 1 ? supports symmetrical & asymmetrical operation ? ctc (common transmit) & itc (independent transmit) clocking modes ? pre-processing of rx icp (ima control protocol) cells ? ima layer & per link statistics and alarms for performance monitoring with mib support tc and uni ? supports mixed-mode operation: links not assigned to an ima group can be used in tc mode ? atm framing using cell delineation 1. mt90222 supports up to 4 serial links with maximum 4 groups to be used - groups 0,1,2,3. MT90223 supports up to 8 serial links mt90224 supports up to 16 serial links ? hec (header error control) verification & generation, error detection, filler cell filtering (ima mode) and idle/unassigned cell filtering (tc mode) ? tc layer statistics and error counts i.e. hec errors with mib support standards compliant ? atm forum - ima 1.1 (af-phy-0086.001) & backwards compatible with ima 1.0 ? atm forum - atm over fractional t1/e1 (af- phy-0130.00) ? itu g.804 cell mapping & itu i.432 cell delineation march 2006 ordering information mt90222ag 384 pin pbga trays mt90224ag 384 pin pbga trays MT90223ag 384 pin pbga trays MT90223ag2 384 pin pbga** trays mt90224ag2 384 pin pbga** traus **pb free tin/silver/copper -40 c to +85 c mt90222/3/4 4/8/16 port ima/tc phy device data sheet figure 1 - mt90222/3/4 block diagram (with built-i n ima functions for up to 8 ima groups over 4/8/16 links) rx external static ram utopia level 2 bus utopia i/f ctrl processor i/f cell cd circuits (1 per link) transmission convergence tc circuits (1 per link) s/p p/s t1/e1/dsl serial tdm ports rx tx tdm ring control tdm ring control tdm ring tdm ring internal ima processors (1 per group) (1 per link, up to 10mb/s delineator rx utopia fifo tx utopia fifo t1/e1/dsl t1/e1/dsl per link)
mt90222/3/4 data sheet 2 zarlink semiconductor inc. general ? supports unframed serial streams up to 10 mb/s per t1/e1 or dsl link ? single chip atm ima & tc processor ? versatile tdm interface for most popular t1 or e1 framers and dsl chipsets ? up to 6 mt90222/3/4 devices can be spanned using a tdm ring supporting 32 links ? provides 8 & 16-bit utopia level 1 & 2 compatible mphy interface (mt90222/3/4 slaved to atm device) ? 16-bit microprocessor interface for intel or motorola ? jtag test support ? 2.5 v core, 3.3 v i/o with 5 v tolerant inputs ? 384 pin pgba with 1.0 mm pitch balls ? mt90222, MT90223 & mt90224 share the same product package and pin-out configuration applications provides cost effective solutions to im plement ima and/or tc functions over t1 , e1, j1 or dsl tr ansport facilities in broadband access networks. typical applications are for trunking or subscriber access in: ? integrated multi-service access platforms ? access multiplexers ? next-generation dlc ? wireless local loop ? 3g wireless base-stations preamble the mt90222, MT90223 and mt90224 form a family of simila r devices, differing mainly in the maximum number of serial links, and are collectively referred to as mt90222/3/ 4. it should be noted throughout this document whenever reference is made to the number of serial links that th e mt90224 offers a maximum of 16 serial links (links 15:0), while the MT90223 offers a maximum of 8 serial links (links 14,12,10,8,6,4,2 and 0), and the mt90222 offers a maximum of 4 serial links (links 12, 8, 4 and 0). pin and register compatibility has been maintained to offer interchangeability. note: when creating ima groups for mt90222 the groups 0, 1, 2 and 3 should be used. description the mt90222/3/4 device is targeted to systems implementing the atm forum inverse multiplexing for atm (ima version 1.1 and 1.0) or uni specifications for t1/e1 rate s. in the mt90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utiliz ation of off-the-shelf, trad itional t1/e1/j1 framers/lius and dsl chip sets. the mt90222/3/4 device can also provid e up to 10 mb/s per link data rates for unframed serial tdm transmissions for xdsl applications. the mt90222/3/4 device provides atm system designers wi th a flexible architectu re when implementing atm access over existing trunk interfaces, allowing a migrat ion towards atm service technology. in addition to the design of atm uni specifications for t1/e1 rates, the mt90222/3/4 device is compliant with the atm forum ima specifications for controlling ima groups of up to 16 trunks in a single chip. the mt90222/3/4 can be configured to operate in different modes to facilitate the implementation of the ima function at both cpe and central office sites. for systems targeting atm over t1/e1 with ima and tc operating simultaneously, the mt90222/3/4 device provides the ideal architecture and capabilities.
mt90222/3/4 data sheet 3 zarlink semiconductor inc. the device provides up to 8 internal ima proc essors and allows for bandwidth scaleability. the implementation of ima as per af-phy-0086.001 inverse multiplexing for atm (ima) specification version 1.1 is divided into hardware and software functions. hardwa re functions are implemented in the mt90222/3/4 device and software functions are implemented by the ima core (z arlink or user) software. a dditional hardware functions are included to assist in the co llection of statistical informati on to support mib implementation. hardware functions that are implemented in the mt90222/3/4 device are: ? utopia level 1 or 2 compatible mphy interface ? incoming hec verification and correction (optional) ? generation of a new hec byte ? format outgoing bytes into multi-vendor tdm formats ? retrieve atm cells from the incoming multi-vendor tdm format ? perform cell delineation ? cell pre-processing ? provide various counters to assist in performance monitoring ? tdm expansion ring to span multiple devices hardware functions that are implemented by the ima processor in the mt90222/3/4 device are: ? transmit scheduler (one per ima group) ? generation of the tx ima data cell rate clock ? generation and insertion of icp cells, filler cells and st uff cells in ima mode and idle cells in tc mode; the icp cells are programmed by the user and t he filler and idle cells are pre-defined ? perform ima frame synchronization ? retrieve and process rx icp cells in ima mode ? management of rx links to be part of the internal re-sequencer when active ? extraction of rx ima data cell rate clock ? verification of delays between links ? perform re-sequencing of atm cells using external asynchronous static ram ? can accommodate more than 200 msec of link diff erential delay depending on the amount of external memory ? provide structured interrupt scheme to report various events
mt90222/3/4 data sheet table of contents 4 zarlink semiconductor inc. 1.0 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.1 software functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.1 link state machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.2 ima group state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.3 link addition, removal or restoration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.5 signalling and rate adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.6 performance monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.2 hardware functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.0 the atm transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.1 cell in control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 the atm transmission convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.1 tx cell ram and tx fifo length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 parallel to serial tdm interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 atm transmit path in ima mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.1 ima frame length (m) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.2 position of the icp cell in the ima frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.3 transmit clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.4 stuff cell rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.5 ima data cell rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.6 ima controller (roundrobin scheduler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.7 icp cell generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.8 ima frame programmable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.9 filler cell definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.10 tx ima group start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.11 tx link addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.12 tx link deletion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 atm transmit path in tc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.0 the atm receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1 cell delineation function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.1 cell delineation with sync signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.2 cell delineation without sync signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.3 de-scrambling and atm cell filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 atm receive path in ima mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.1 icp cell processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.2 ima frame synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.3 link information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.4 rx oam label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.5 out of ima frame (oif) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.6 loss of ima frame (lif) synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.7 filler cell handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.8 stuff cell handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.9 received icp cell buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.10 rate recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.11 cell buffer/ram controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.12 cell sequence recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.13 delay between links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.13.1 rx recombiner delay value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.13.2 rx maximum operational delay value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.13.3 link out of delay synchronization (lods) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.13.4 negative delay values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.13.5 measured delay between links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
mt90222/3/4 data sheet table of contents 5 zarlink semiconductor inc. 3.2.13.6 incrementing/decrementing the recombiner delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.14 rx ima group start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.15 link addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.16 link deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.17 disabling an ima group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3 the atm receive path in tc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.0 description of the tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.1 single mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1.1 single mode - generic 1.544 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1.2 single mode - generic 2.048 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1.3 single mode -st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2 wire-or mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.1 wire-or mode - 2 link grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.2 wire-or mode - 4 link grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 multiplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.1 multiplex mode - 2 link multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.2 multiplex mode - 4 link multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4 non-framed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.1 non-framed mode - 2.5 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.2 non-framed mode - 5.0 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4.3 non-framed mode - 10.0 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.5 clock formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 tdm loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.7 serial to parallel (s/p) and parallel to serial (p/s) converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.8 clocking options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8.1 verification of the rxsync period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8.2 verification of the txsync period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8.3 primary and secondary reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8.4 verification of clock activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.8.5 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.0 utopia interface operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1 atm input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 atm output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3 utopia operation with a single phy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4 utopia operation with multiple phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.5 utopia operation in tc mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6 utopia operation in ima mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.7 utopia loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.8 examples of utopia operations modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.0 support blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1 counter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.1 utopia input i/f counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.2 transmit tdm i/f counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.3 receive tdm i/f counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.1.4 access to the counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.1.5 latching counter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 interrupt block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2.1 irq master status and irq master enable registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2.2 irq link status and irq link enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.2.2.1 bit 8 and 7 of irq link 0 st atus and irq link 0 enable registers. . . . . . . . . . . . . . . . . . . . 70 6.2.3 irq link tc overflow status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2.4 irq ima group overflow status and enable registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
mt90222/3/4 data sheet table of contents 6 zarlink semiconductor inc. 6.2.5 irq ima overflow status and rx utopia ima gr oup fifo overflow enable registers . . . . . . . 71 6.3 microprocessor interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.1 access to the various registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.2 direct access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.3 indirect access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.4 clearing of status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.4.1 toggle bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4 cell preprocessor block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.5 tdm ring block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.6 sram decoding for mt90222/223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.0 register descriptions:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.1 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.0 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.1 connecting the mt90222/3/4 to various t1/e1/j1 framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 8.2 connecting the mt90222/3/4 to shdsl framers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.0 ac/dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.1 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.0 list of abbreviations and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.0 atm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
mt90222/3/4 data sheet list of figures 7 zarlink semiconductor inc. figure 1 - mt90222/3/4 block diagram (with built-in ima func tions for up to 8 ima groups over 4/8/16 links) . . . 1 figure 2 - mt90222 pinout (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 - MT90223 pinout (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 - mt90224 pinout (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5 - mt90224 functional block diagram -transmitter in ima mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6 - functional block diagram of the transmitter in tc mode (for link[n], 0 n 15) . . . . . . . . . . . . . . . 41 figure 7 - cell delineation state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 8 - sync state block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9 - mt90224 receiver circuit in ima mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 10 - example of tc mode operation (using four of sixteen possible utopia-output ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 11 - single mode - generic 1.544 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12 - single mode - generic 2.048 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 13 - single mode - st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 14 - txck and txsync output pin source options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 15 - atm interface to mt90224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 16 - atm interface to multiple mt90224s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 17 - atm mixed-mode interface to one mt90224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 18 - irq register hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19 - processed rx cell fifo word format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 20 - synchronous st-bus mode (using st-bus/2.048 mbps backplane compatible framers) . . . . . . 125 figure 21 - ctc mode (using mt9076b t1/e1/j1 single chip transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 22 - itc mode with st-bus (using zarlink mt9076b t1/e1/j1 single chip transceivers) . . . . . . . . . . 127 figure 23 - itc mode with generic tdm interface (using mt90 76b t1/e1/j1 framer/liu) . . . . . . . . . . . . . . . 128 figure 24 - asynchronous operations (using two mt9072 octal t1/e1/j1 framers) . . . . . . . . . . . . . . . . . . . . 129 figure 25 - interface to shdsl device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 26 - setup and hold time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 27 - tri-state timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 28 - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 29 - external memory interface timing - read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 30 - external memory interface timing - write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 31 - cpu interface motorola timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 32 - cpu interface intel timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 33 - cpu interface motorola timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 34 - cpu interface intel timing - write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 35 - st-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 36 - generic bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 37 - tdm ring tx timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 38 - tdm ring rx timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 39 - jtag port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 40 - system clock and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
mt90222/3/4 data sheet list of tables 8 zarlink semiconductor inc. table 1 - idcr integration register value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 2 - icp cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 3 - cell acquisition time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 4 - differential delay for various memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5 - conversion factors time/cell (msec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 6 - register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 7 - utopia output link address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 8 - utopia output group address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 9 - utopia output link phy enable registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 10 - utopia output group phy enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 11 - utopia output user defined byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 12 - utopia input link address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 13 - utopia input group address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 14 - utopia input link phy enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 15 - utopia input group phy enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 16 - utopia input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 17 - utopia input parity error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 18 - tx cell ram control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 19 - tx icp cell handler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 20 - tx ima frame indication register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 21 - tx icp cell interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 22 - tx ima frame interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 23 - tx link fifo length definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 24 - tx ima group fifo length definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 25 - tx fifo length status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 26 - rx link control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 27 - loss of delineation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 28 - cell delineation register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 29 - ima frame delineation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 30 - user defined rx oam label register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 31 - rx oif status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 32 - rx oif counter clear command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 33 - rx wrong filler status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 34 - rx load values/link select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 35 - rx oam label register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 36 - rx link ima id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 37 - rx icp cell offset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 38 - rx link frame sequence number register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 39 - rx link scci sequence number register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 40 - rx link oif counter value register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 41 - rx link id number register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 42 - rx state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 43 - ima frame state machine status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 44 - cell delineation status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 45 - rx cell type ram register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 46 - rx cell type ram register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 47 - rx cell process enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 48 - rx cell buffer increment read pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
mt90222/3/4 data sheet list of tables 9 zarlink semiconductor inc. table 49 - rx cell level fifo status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 50 - processed rx cell link fifo status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 51 - icp cell ram debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 52 - processed rx cell link fifo register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 53 - ring tx control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 54 - ring tx link registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 55 - ring rx link registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 56 - rx recombiner registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 57 - rx reference link control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 58 - rx idcr integration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 59 - rx external sram access control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 60 - increment delay control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 61 - decrement delay control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 62 - rx recombiner delay control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63 - rx external sram read/write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 64 - rx delay register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 65 - rx delay link number register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 66 - rx guardband/delta delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 67 - rx external sram read/write address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 68 - rx external sram read/write address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 69 - sram control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 70 - rx maximum operational delay register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 71 - rx delay select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 72 - enable recombiner status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 73 - tx group control mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 74 - tx icp cell offset registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 75 - tx link control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 76 - tx ima control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 77 - tx add link control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 78 - tx link id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 79 - tx link active status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 80 - tx ima mode status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 81 - utopia input cell counter groups register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 82 - utopia input cell counter links register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 83 - tx idcr integration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 84 - irq ima group overflow enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 85 - rx utopia ima group fifo overflow irq enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 table 86 - general status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 87 - counter transfer command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 88 - irq link tc overflow status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 89 - irq ima overflow status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 90 - counter upper byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 91 - counter bytes 2 and 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 92 - select counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 93 - irq master enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 94 - irq link tc overflow enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 95 - irq link status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 96 - irq link enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
mt90222/3/4 data sheet list of tables 10 zarlink semiconductor inc. table 97 - irq master status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 98 - irq ima group overflow status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 99 - tx ima icp cell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 100 - tdm tx link control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 101 - tdm tx mapping (timeslots 15:0) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 102 - tdm tx mapping (timeslots 31:16) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 103 - txck status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 104 - rxck status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 105 - refck status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 106 - tx sync. status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 107 - pll reference control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 108 - tdm rx link control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 109 - tdm rx mapping (timeslots 15:0) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 110 - tdm rx mapping (timeslots 31:16) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 111 - rx sync. status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 112 - rx automatic atm synchronization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 113 - rx ima icp cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
mt90222/3/4 data sheet 11 zarlink semiconductor inc. pin diagram - mt90222 the mt90222 uses a 384 pin pbga with a 1.0 mm ball pitch. figure 2 - mt90222 pinout (bottom view) 2625242322212019181716151413121110987654321 a dsti[4] nc vdd5 nc nc rxsyn ci[0] txring- data[1] txring- data[5] txring- sync sr_cs_1 sr_a[1] sr_a[4] vdd5 sr_a[7] sr_a [11] sr_a [15] sr_a [18] vdd5 sr_d[6] nc tms reset nc nc a b nc vss rxsyn ci[4] nc ic nc dsti[0] txring- data[0] txring- data[4] txring- data[7] sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a [12] sr_a [16] sr_d[0] sr_d[3] sr_d[7] tdi trst tes t 4 n c vs s n c b c nc nc vss rxcki [4] nc ic rxcki [0] latch clk txring- data[2] txring- data[6] vdd5 nc sr_a[2] sr_a[6] sr_a [10] sr_a [14] sr_a [17] sr_d [1] sr_d[4] test3 tdo vdd5 nc vss urx data[0] urx data[2] c d ic nc nc vss v3.3 nc vdd5 test2 txring- data[3] v2.5 txring- clk sr_we v3.3 v2.5 sr_a[9] sr_a [13] v3.3 sr_d[2] sr_d[5] tck v3.3 vss vss urx data[1] urx data[3] urx data[4] d e nc nc nc v3.3 vss urx data[5] vdd5 urx data[6] e f vdd5 nc ic nc v3.3 urx data[7] urx data[8] urx data[9] f g rxcki [8] dsti[8] nc rxsyn ci[8] urxd ata[10] urxd ata[11] urxd ata[12] urxd ata[13] g h vdd5 nc nc nc urxd ata[14] urxd ata[15] urx par vdd5 h j nc ic ic nc urx soc urx clav nc vdd5 j k rxsyn ci[12] nc nc v3.3 v2.5 urx- clk urx enb urxa ddr[0] k l nc rxcki [12] dsti [12] nc vss vss vss vss vss vss urxa ddr[2] urxa ddr[1] urxa ddr[3] urxa ddr[4] l m nc ic nc nc vss vss vss vss vss vss utx data[0] vdd5 utx data[1] nc m n nc vdd5 ic v2.5 vss vss vss vss vss vss v3.3 utx data[2] utx data[3] utx data[4] n p nc nc nc v3.3 vss vss vss vss vss vss v2.5 utx data[6] vdd5 utx data[5] p r pd pd nc nc vss vss vss vss vss vss utx data[9] utxd ata[10] utxd ata[8] utxd ata[7] r t pd pd pd nc vss vss vss vss vss vss utxd ata[13] vdd5 utxd ata[12] utxd ata[11] t u pd dsto [12] txckio [12] v2.5 v3.3 utxpar utxd ata[15] utxd ata[14] u v vdd5 txsyn cio[12] nc pd utxclk utx enb utx clav utx soc v w pd nc pd pd utx addr[2] utx addr[3] utx addr[1] utx addr[0] w y nc pd pd dsto [8] utx addr[4] refck [0] vdd5 nc y aa txckio [8] vdd5 txsyn cio[8] v3.3 refck [2] refck [3] nc refck [1] aa ab nc pd pd vss v3.3 vdd5 pll ref[1] pll ref[0] ab ac nc pd nc vss v3.3 pd nc vdd5 nc v3.3 rxring data[7] rxring data[4] v2.5 v3.3 up_a [10] up_a[7] v2.5 up_irq nc up_d [10] v3.3 vss vss nc nc clk ac ad pd vdd5 vss nc nc nc txsyn cio[4] pd pd dsto [0] txsyn cio[0] vdd5 rxring data[1] up_oe or up_rd vdd5 up_a[6] up_a[3] up_a[0] up_d [14] up_d [11] up_d[8] up_d[5] up_d[2] vss nc test1 ad ae nc vss nc nc pd dsto [4] nc nc pd nc rxring data[6] rxring data[3] rxring data[0] up_cs up_a [11] up_a[8] up_a[4] up_a[1] up_d [15] up_d [12] vdd5 up_d[6] up_d[4] up_d[1] vss nc ae af nc nc nc nc txckio [4] pd pd pd txckio [0] rxring data[5] rxring data[2] rxring sync rxring clk up_r/w or up_wr up_a[9] up_a[5] up_a[2] vdd5 up_d [13] up_d[9] up_d[7] nc up_d[3] up_d[0] af 2625242322212019181716151413121110987654321
mt90222/3/4 data sheet 12 zarlink semiconductor inc. pin diagram - MT90223 the MT90223 uses a 384 pin pbga with a 1.0 mm ball pitch. figure 3 - MT90223 pinout (bottom view) 2625242322212019181716151413121110987654321 a dsti[4] nc vdd5 dsti[2] nc rxsyn ci[0] txring- data[1] txring- data[5] txring- sync sr_cs_1 sr_a[1] sr_a[4] vdd5 sr_a[7] sr_a[11] sr_a[15] sr_a[18] vdd5 sr_d[6] nc tms reset nc nc a b nc vss rxsyn ci[4] nc rxcki [2] nc dsti[0] txring- data[0] txring- data[4] txring- data[7] sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a[12] sr_a[16] sr_d[0] sr_d[3] sr_d[7] tdi trst tes t 4 n c v ss n c b c nc nc vss rxcki [4] nc rxsyn ci[2] rxcki [0] latch- clk txring- data[2] txring- data[6] vdd5 nc sr_a[2] sr_a[6] sr_a[10] sr_a[14] sr_a[17] sr_d[1] sr_d[4] test3 tdo vdd5 nc vss urx- data[0] urx- data[2] c d rxsyn ci[6] nc nc vss v3.3 nc vdd5 test2 txring- data[3] v2.5 txring- clk sr_we v3.3 v2.5 sr_a[9] sr_a[13] v3.3 sr_d[2] sr_d[5] tck v3.3 vss vss urx- data[1] urx- data[3] urx- data[4] d e dsti[6] nc nc v3.3 vss urx- data[5] vdd5 urx- data[6] e f vdd5 nc rxcki [6] nc v3.3 urx- data[7] urx- data[8] urx- data[9] f g rxcki [8] dsti[8] nc rxsyn ci[8] urx- data[10 ] urx- data[11] urx- data[12 ] urx- data[13 ] g h vdd5 nc nc nc urx- data[14 ] urx- data[15 ] urxpar vdd5 h j nc rxcki [10] rxsyn ci[10] dsti[10 ] urx- soc urx- clav nc vdd5 j k rxsyn ci[12] nc nc v3.3 v2.5 urxclk urxenb urxa- ddr[0] k l nc rxcki [12] dsti[12 ] nc vss vss vss vss vss vss urxa- ddr[2] urxa- ddr[1] urxa- ddr[3] urxa- ddr[4] l m dsti[14 ] rxsyn ci[14] nc nc vss vss vss vss vss vss utx- data[0] vdd5 utx- data[1] nc m n nc vdd5 rxcki [14] v2.5 vss vss vss vss vss vss v3.3 utx- data[2] utx- data[3] utx- data[4] n p nc nc nc v3.3 vss vss vss vss vss vss v2.5 utx- data[6] vdd5 utx- data[5] p r pd pd nc dsto[1 4] vss vss vss vss vss vss utx- data[9] utx- data[10 ] utx- data[8] utx- data[7] r t txckio [14] txsyn- cio[14] pd nc vss vss vss vss vss vss utx- data[13 ] vdd5 utx- data[12 ] utx- data[11] t u pd dsto[1 2] txckio [12] v2.5 v3.3 utxpar utx- data[15 ] utx- data[14 ] u v vdd5 txsyn- cio[12] nc pd utxclk utxenb utx- clav utx- soc v w pd dsto[1 0] txckio [10] txsyn- cio[10] utx- addr[2] utx- addr[3] utx- addr[1] utx- addr[0] w y nc pd pd dsto[8] utx- addr[4] refck [0] vdd5 nc y aa txckio [8] vdd5 txsyn- cio[8] v3.3 refck [2] refck [3] nc refck [1] aa ab nc pd pd vss v3.3 vdd5 pll- ref[1] pll- ref[0] ab ac dsto[6] txckio [6] nc vss v3.3 pd nc vdd5 nc v3.3 rxring data[7] rxring data[4] v2.5 v3.3 up_a[10 ] up_a[7] v2.5 up_irq nc up_d[10 ] v3.3 vss vss nc nc clk ac ad txsyn- cio[6] vdd5 vss nc nc nc txsyn- cio[4] pd txsyn- cio[2] dsto[0] txsyn- cio[0] vdd5 rxring data[1] up_oe or up_rd vdd5 up_a[6] up_a[3] up_a[0] up_d[14 ] up_d[11 ] up_d[8] up_d[5] up_d[2] vss nc test1 ad ae nc vss nc nc pd dsto[4] nc dsto[2] pd nc rxring data[6] rxring data[3] rxring data[0] up_cs up_a[11 ] up_a[8] up_a[4] up_a[1] up_d[15 ] up_d[12 ] vdd5 up_d[6] up_d[4] up_d[1] vss nc ae af nc nc nc nc txckio [4] pd txckio [2] pd txckio [0] rxring data[5] rxring data[2] rxring sync rxring clk up_r/w or up_wr up_a[9] up_a[5] up_a[2] vdd5 up_d[13 ] up_d[9] up_d[7] nc up_d[3] up_d[0] af 2625242322212019181716151413121110987654321
mt90222/3/4 data sheet 13 zarlink semiconductor inc. pin diagram - mt90224 the mt90224 uses a 384 pin pbga with a 1.0 mm ball pitch. figure 4 - mt90224 pinout (bottom view) 2625242322212019181716151413121110987654321 a dsti[4] rxcki [3] vdd5 dsti[2] rxsyn ci[1] rxsyn ci[0] txring- data[1] txring- data[5] txring- sync sr_cs_1 sr_a[1] sr_a[4] vdd5 sr_a[7] sr_a [11] sr_a [15] sr_a [18] vdd5 sr_d[6] nc tms reset nc nc a b nc vss rxsyn ci[4] dsti[3] rxcki [2] dsti[1] dsti[0] txring- data[0] txring- data[4] txring- data[7] sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a [12] sr_a [16] sr_d[0] sr_d[3] sr_d[7] tdi trst te s t 4 n c v s s n c b c dsti[5] nc vss rxcki [4] rxsyn ci[3] rxsyn ci[2] rxcki [0] latch clk txring- data[2] txring- data[6] vdd5 nc sr_a[2] sr_a[6] sr_a [10] sr_a [14] sr_a [17] sr_d [1] sr_d[4] test3 tdo vdd5 nc vss urx data[0] urx data[2] c d rxsyn ci[6] rxsyn ci[5] nc vss v3.3 rxcki [1] vdd5 test2 txring- data[3] v2.5 txring- clk sr_we v3.3 v2.5 sr_a[9] sr_a [13] v3.3 sr_d[2] sr_d[5] tck v3.3 vss vss urx data[1] urx data[3] urx data[4] d e dsti[6] nc rxcki [5] v3.3 vss urx data[5] vdd5 urx data[6] e f vdd5 dsti[7] rxcki [6] rxsyn ci[7] v3.3 urx data[7] urx data[8] urx data[9] f g rxcki [8] dsti[8] rxcki [7] rxsyn ci[8] urxd ata[10] urxd ata[11] urxd ata[12] urxd ata[13] g h vdd5 rxcki [9] rxsyn ci[9] dsti[9] urxd ata[14] urxd ata[15] urx par vdd5 h j rxsyn ci[11] rxcki [10] rxsyn ci[10] dsti [10] urx soc urx clav nc vdd5 j k rxsyn ci[12] rxcki [11] dsti [11] v3.3 v2.5 urx- clk urx enb urxa ddr[0] k l rxsyn ci[13] rxcki [12] dsti [12] nc vss vss vss vss vss vss urxa ddr[2] urxa ddr[1] urxa ddr[3] urxa ddr[4] l m dsti [14] rxsyn ci[14] dsti [13] rxcki [13] vss vss vss vss vss vss utx data[0] vdd5 utx data[1] nc m n rxsyn ci[15] vdd5 rxcki [14] v2.5 vss vss vss vss vss vss v3.3 utx data[2] utx data[3] utx data[4] n p dsti [15] rxcki [15] dsto [15] v3.3 vss vss vss vss vss vss v2.5 utx data[6] vdd5 utx data[5] p r txckio [15] txsyn cio[15] nc dsto [14] vss vss vss vss vss vss utx data[9] utxd ata[10] utxd ata[8] utxd ata[7] r t txckio [14] txsyn cio[14] txckio [13] dsto [13] vss vss vss vss vss vss utxd ata[13] vdd5 utxd ata[12] utxd ata[11] t u txsyn cio[13] dsto [12] txckio [12] v2.5 v3.3 utxpar utxd ata[15] utxd ata[14] u v vdd5 txsyn cio[12] dsto [11] txckio [11] utxclk utx enb utx clav utx soc v w txsyn cio[11] dsto [10] txckio [10] txsyn cio[10] utx addr[2] utx addr[3] utx addr[1] utx addr[0] w y dsto [9] txckio [9] txsyn cio[9] dsto [8] utx addr[4] refck [0] vdd5 nc y aa txckio [8] vdd5 txsyn cio[8] v3.3 refck [2] refck [3] nc refck [1] aa ab dsto [7] txckio [7] txsyn cio[7] vss v3.3 vdd5 pll ref[1] pll ref[0] ab ac dsto [6] txckio [6] dsto [5] vss v3.3 txsyn cio[5] nc vdd5 dsto [1] v3.3 rxring data[7] rxring data[4] v2.5 v3.3 up_a [10] up_a[7] v2.5 up_irq nc up_d [10] v3.3 vss vss nc nc clk ac ad txsyn cio[6] vdd5 vss nc nc nc txsyn cio[4] txsyn cio[3] txsyn cio[2] dsto [0] txsyn cio[0] vdd5 rxring data[1] up_oe or up_rd vdd5 up_a[6] up_a[3] up_a[0] up_d [14] up_d [11] up_d[8] up_d[5] up_d[2] vss nc test1 ad ae nc vss nc nc txckio [5] dsto [4] dsto [3] dsto [2] txckio [1] nc rxring data[6] rxring data[3] rxring data[0] up_cs up_a [11] up_a[8] up_a[4] up_a[1] up_d [15] up_d [12] vdd5 up_d[6] up_d[4] up_d[1] vss nc ae af nc nc nc nc txckio [4] txckio [3] txckio [2] txsyn cio[1] txckio [0] rxring data[5] rxring data[2] rxring sync rxring clk up_r/w or up_wr up_a[9] up_a[5] up_a[2] vdd5 up_d [13] up_d[9] up_d[7] nc up_d[3] up_d[0] af 2625242322212019181716151413121110987654321
mt90222/3/4 data sheet 14 zarlink semiconductor inc. mt90222 pin description pin # name i/o description atm input port signals (utopia transmit interface) u2,u1,t4,t2, t1,r3,r4,r2,r 1,p3,p1,n1,n2, n3,m2,m4 utxdata [15:0] i utopia transmit data bus. 16 (or 8) bit wide data driven from atm layer device to mt90222. bit 15 (or 7) is the msb. all arriving data between the last word (byte) of the previous cell and the first word (byte) of the following cell (indicated by the soc signal) is ignored. utxdata[15:8] have internal weak pull-downs. u3 utxpar i utopia transmit parity. odd (or even) parity bit generated by the atm layer. the parity bit is sampled on the rising edge of utxclk. utxpar has an internal weak pull-down. v1 utxsoc i utopia transmit start of cell signal. active high signal asserted by the atm layer device when txdata[15:0] ([7:0]) contains the first valid word (byte) of the cell. after this signal is high, the following 26 word (52 bytes) should contain valid data. the mt90222 waits for another txsoc and txenb signal after reading a complete cell. an external pull-down(4.7 k) is strongly recommended. v4 utxclk i utopia transmit clock. transfer clock from the atm layer device to the mt90222 which synchronizes data transfers on txdata[15:0] ([7:0]). this signal is the clock of the incoming data. data is sampled on the rising edge of this signal.for 8-bit utopia mode the maximum supported clock is 52 mhz and for 16-bit utopia mode maximum supported clock is 33 mhz. v3 utxenb i utopia transmit data enable. active low signal asserted by the atm layer device during cycles when txdata contains valid cell data. v2 utxclav o utopia transmit cell available signal. for cell-level flow control in a mphy environment, txclav is an active high tri-stateable signal from the mt90222 to the atm layer device. y4,w3,w4, w2,w1 utxaddr [4:0] i transmit address . five bit wide address bus driven by the atm layer device to poll and select the appropriate phy address. txaddr[4] is the msb. atm output port signals (utopia receive interface) h3,h4,g1,g2,g 3,g4,f1,f2, f3,e1,e3,d1, d2,c1,d3,c2 urxdata [15:0] o utopia receive data bus. 16 (or 8) bit wide data driven from mt90222 to atm layer device. rxdata[15] ([7]) is the msb. to support multiple phy configurations, rxdata is driven only when rxenb and port is selected. it is tri-stated otherwise. h2 urxpar o utopia receive parity. odd (or even) parity bit generated by the mt90222 to the atm layer. j4 urxsoc o utopia receive start of cell signal. active high asserted by the mt90222 when rxdata contains the first valid word (byte) of a cell. k3 urxclk i utopia receive clock . this signal is the clock driven from the atm layer to the phy layer. data changes after the rising edge of this signal. k2 urxenb i utopia receive data enable. active low signal asserted by the atm layer device to indicate that urxdata[15:0] ([7:0]) and urxsoc will be sampled at the end of the next cycle. in multiple phy configurations, urxenb is used to tri-state urxdata and urxsoc mt90222 outputs. in this case, urxdata and urxsoc would be enabled only in cycles following those with urxenb asserted. in utopia l1, urxenb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer. j3 urxclav o utopia receive cell available signal. for cell-level flow control in a mphy environment, urxclav is an active high tri-stateable signal from the mt90222 to atm layer device. l1, l2, l4, l3, k1 urxaddr [4:0] i receive address . five bit wide address bus driven from the atm to phy device to select the appropriate phy address. urxaddr[4] is the msb. receiver static memory interface signals
mt90222/3/4 data sheet 15 zarlink semiconductor inc. b7,a7,d8,c8, b8,d9,c9,b9 sr_d [7:0] i/o static memory data bus . data bus to exchange data between the mt90222 and the external static memory. sr_d[7:0] has internal weak pull-downs. a9,c10,b10, a10,c11,d11,b 11,a11,c12,d1 2,b12,a12,c13, b13,a14,b14,c 14,a15,b15 sr_a [18:0] o static memory address bus . address bus on the external static memory. d15 sr_we o static memory read/not write . if low, data is written from the mt90222 to the memory. if high, data is read from the memory to the mt90222. a16,b16 sr_cs_1, 0 o static memory chip select signal. active low. processor interface signals ae8,ad8,af7, ae7,ad7,ac7, af6,ad6,af5,a e5,ad5,ae4,a f3,ad4,ae3,af 2 up_d [15:0] i/o processor data bus . data bus to exchange data between the mt90222 and a local processor. ae12,ac12, af11,ae11, ac11,ad11, af10,ae10, ad10,af9, ae9,ad9 up_a [11:0] i processor address bus . used to select the internal registers and memory locations of the mt90222. af12 up_r/w or up_wr i processor read/not write (motorola mode). this is an input signal. if low, data is written from the processor to the mt90222. if high, data is read from the mt90222 to the processor. processor not write (intel mode). this is an input signal, active low. if low, data is written from the processor to the mt90222. ad13 up_oe or up_rd i output enable (motorola mode). this is an input signal. this signal should be tied to gnd for motorola timing mode. processor read (intel mode). this is an input signal, active low. if low, data is read from the mt90222. ae13 up_cs i chip select . this is an active low input signal. if this signal is high, the mt90222 ignores all other signals on its processor bus. if this signal is low, the mt90222 accepts the signals on its processor bus. ac9 up_irq o processor interrupt request . open drain signal. if this signal is low, the mt90222 signals to the processor that an interrupt condition is pending inside the mt90222. tdm interface signals u25, y23, ae21, ad17 dsto [12] [8] [4] [0] o serial tdm data output 12, 8, 4 and 0 . serial stream which contains transmit data. the output is set to high impedance for unused time slots and if the link is not used. it is aligned with txckio and txsyncio. l24, g25, a25, b20 dsti [12] [8] [4] [0] i serial tdm data input 12, 8, 4 and 0 . serial stream which contains receive data. it is aligned with rxcki and rxsynci. these pins have internal weak pull-downs. mt90222 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 16 zarlink semiconductor inc. u24, aa26, af21, af17 txckio [12] [8] [4] [0] i/o tdm interface transmit clock 12, 8, 4 and 0. this pin is an input or an output as selected by the tdm tx link control registers. the txck source is software selectable and can be either one of the four rxck or one of the four refck signals when defined as output. when defined as input, the proper clock signal is provided to the input pin. the clock polarity is determined by the tdm tx link control registers. these pins have internal weak pull-downs. v25, aa24, ad20, ad16 txsyncio [12] [8] [4] [0] i/o transmit line frame pulse 12, 8, 4 and 0 . this pin is an input or an output as selected by the tdm tx link control registers. it is the frame reference (typically 8 khz) used as transmit synchronization for the tdm system interface. when an output, the txsync is generated from the txck signal and is independent from other txsync signals. two major modes are available: generic and st-bus: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32/64/128 channel frame of the st-bus interface at dsti and dsto lines. 2. for generic tdm interfaces, it can be programmed to generate or receive either a positive or negative pulse polarity that marks the first bit of the tdm system interface. these pins have internal weak pull-downs. k26, g23, b24, a20 rxsynci [12] [8] [4] [0] i receive line frame pulse 12, 8, 4 and 0 . this is the frame reference (typically 8 khz) used as receive synchronization for the tdm system interface. two major modes are available: generic and st-bus: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32/64/128 channel frame of the st-bus interface at dsti and dsto lines. 2. for generic tdm interfaces, it can be programmed to accept either a positive or negative pulse polarity that marks the first bit of the tdm system interface. these pins have internal weak pull-downs. l25, g26, c23, c20 rxcki [12] [8] [4] [0] i tdm interface receive clock 12, 8, 4 and 0. this input line represents the clock for the receive serial tdm data. the expected frequency value to be received at this input clock is defined by the user through the rx link tdm control register. these pins have internal weak pull-downs. ab2,ab1 pllref [1:0] o output reference to an external pll . aa3,aa4, aa1,y3 refck [3:0] i input reference clock inputs 3 to 0. receive the de-jittered transmit clock reference to be internally routed to the txckio tran smit clocks. these pins have internal weak pull-downs. tdm ring signals d16 txringclk o tdm ring tx clock. clock output signal used to align the txringsync and txringdata. should be connected to the rxringclk input of the next mt90222 device in the ring. this output is in high z state if the tdm ring is not used. not 5 v tolerant. a17 txring sync o tdm ring tx sync. synchronization output signal used to retrieve data and control from the bytes on txringdata. should be connected to the rxringsync input of the next mt90222 device in the ring. this output is in high z state if the tdm ring is not used. not 5 v tolerant. b17,c17,a18,b 18,d18,c18,a1 9,b19 txring data[7:0] o tdm ring tx data[7:0]. data bus connecting the tx tdm ring port to the rx tdm ring port. should be connected to the rxringdata inputs of the next mt90222 device in the ring. these output are in high z state if the tdm ring is not used. not 5 v tolerant. af13 rxringclk i tdm ring rx clock. clock input signal used to align the rxringsync and rxringdata. should be connected to the txringclk input of the previous mt90222 device in the ring. there is an internal weak pull-down on this input. not 5 v tolerant. mt90222 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 17 zarlink semiconductor inc. af14 rxring sync i tdm ring rx sync. synchronization input signal used to retrieve data and control from the bytes on rxringdata. should be connected to the txringsync output of the previous mt90222 device in the ring. there is an internal weak pull-down on this input. not 5 v tolerant. ac16,ae16, af16,ac15, ae15,af15, ad14,ae14 rxring data[7:0] i tdm ring rx data[7:0]. data bus connecting the rx tdm ring port to the tx tdm ring port. should be connected to the txringdata inputs of the previous mt90222 device in the ring. there are internal weak pull-downs on these inputs. not 5 v tolerant. system signals ac1 clk i system clock (50 mhz nominal) . in the mt90222, this clock is used for all internal operations of the device. c19 latchclk i counter latch clock. the clock present at this input can be divided internally to produce the latch signal for the internal counters. refer to the counter transfer command register for more details. this pin has an internal pull-down. a4 reset i system reset. this is an active low input signal. it causes the device to enter the initial state. the clk signal must be active to reset the internal registers. d7 tck i jtag test clock. tck should be pulled down if not used. a5 tms i jtag test mode select . tms is sampled on the rising edge of tck. b6 tdi i jtag test data input . this pin has an internal weak pull-down. c6 tdo o jtag test data output . note: tdo is tristated by trst pin. b5 trst i jtag test reset (active low). should be asserted low on power-up and during reset. must be high for jtag boundary-scan operation. this pin has an internal weak pull-down. ad1 test1 i test1. must be tied low d19 test2 o test2 . must be left not connected (nc). c7 test3 i test3 . must be pulled up to v3.3 for normal operation. not 5 v tolerant. b4 test4 o test4 . must be left not connected (nc) power signals e2,h1,j1,m3, p2,t3,y2,ab3, ae6,af8, ad12,ad15, ac19,ad25, aa25,v26, n25,h26,f26,a 23,d20,c16,a1 3,a8,c5 vdd5 s 5 volt supply pin . connect to a 5 volt supply when interfacing to 5 volt signals, otherwise, connect to a 3.3 volt supply. aa23,ab04, ac06,ac13, ac17,ac22, d6,d10,d14, d22,e23,f4, k23,n4,p23, u4 v3.3 s 3.3 volt supply pin for i/o pins. connect to a 3.3 volt supply. d13,d17,n23,u 23,ac10, ac14,k4,p4 v2.5 s 2.5 volt supply for core. connect to a 2.5 volt power supply. mt90222 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 18 zarlink semiconductor inc. ab23,ac4, ac5,ac23, ad3,ad24, ae2,ae25,b2,b 25,c3,c24, d4,d5,d23,e4, l11,l12,l13, l14,l15,l16, m11,m12,m13, m14,m15,m16, n11,n12,n13,n 14,n15,n16,p1 1,p12,p13,p14, p15,p16,r11,r 12,r13,r14,r1 5,r16,t11,t12, t13, t14,t15,t16 vss s ground. b1,j2,m1,y1, aa2,ac2,ad2, ae1,ac3,af4, ac8,ae17, ac20,ad21, af22,af23, ad22,ae23, af24,ae24, af25,ad23, ae26,r24, l23,e25,c25, b26,d24,c15,a 6,a3,c4, b3,a2, p24,t23, v24,y26, ab26, ac24, ae20, ac18 r23, w25, ac26, ae19, p26, m24, k24, h23, f25, c26, b23, b21, m26, j23, e26,a22, n26, l26, j26, h24, f23, d25, c22, a21, p25, m23, k25, h25, g24, e24, a24, d21 nc i not connected. mt90222 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 19 zarlink semiconductor inc. r26, t24, v23, y25, ab25, ae22, af20, ae18, t26, w24, ac25, af19, r25, u26, w26, y24, ab24, ac21, ad19, af18, t25, w23, ad26,ad18 pd i/o pull down. connect to vss via a high va lue resistor, e.g., 10 k ohm. m25, j24, d26, c21 n24, j25, f24, b22 ic i internal connection . connect directly vss. mt90222 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 20 zarlink semiconductor inc. MT90223 pin description pin # name i/o description atm input port signals (utopia transmit interface) u2,u1,t4,t2, t1,r3,r4,r2, r1,p3,p1,n1, n2,n3,m2,m4 utxdata [15:0] i utopia transmit data bus. 16 (or 8) bit wide data driven from atm layer device to MT90223. bit 15 (or 7) is the msb. all arriving data between the last word (byte) of the previous cell and the first word (byte) of the following cell (indicated by the soc signal) is ignored. utxdata[15:8] have internal weak pull-downs. u3 utxpar i utopia transmit parity. odd (or even) parity bit generated by the atm layer. the parity bit is sampled on the rising edge of utxclk. utxpar has an internal weak pull-down. v1 utxsoc i utopia transmit start of cell signal. active high signal asserted by the atm layer device when txdata[15:0] ([7:0]) contains the first valid word (byte) of the cell. after this signal is high, the following 26 word (52 bytes) should contain valid data. the MT90223 waits for another txsoc and txenb signal after reading a complete cell.an external pull-down (4.7 k) is strongly recommended. v4 utxclk i utopia transmit clock. transfer clock from the atm layer device to the MT90223 which synchronizes data transfers on txdata[15:0] ([7:0]). this signal is the clock of the incoming data. data is sampled on the rising edge of this signal.for 8-bit utopia mode the maximum supported clock is 52 mhz and for 16-bit utopia mode maximum supported clock is 33 mhz. v3 utxenb i utopia transmit data enable. active low signal asserted by the atm layer device during cycles when txdata contains valid cell data. v2 utxclav o utopia transmit cell available signal. for cell-level flow control in a mphy environment, txclav is an active high tri-stateable signal from the MT90223 to the atm layer device. y4,w3,w4, w2,w1 utxaddr [4:0] i transmit address . five bit wide address bus driven by the atm layer device to poll and select the appropriate phy address. txaddr[4] is the msb. atm output port signals (utopia receive interface) h3,h4,g1,g2,g 3,g4,f1,f2, f3,e1,e3,d1, d2,c1,d3,c2 urxdata [15:0] o utopia receive data bus. 16 (or 8) bit wide data driven from MT90223 to atm layer device. rxdata[15] ([7]) is the msb. to support multiple phy configurations, rxdata is driven only when rxenb and port is selected. it is tri-stated otherwise. h2 urxpar o utopia receive parity. odd (or even) parity bit generated by the MT90223 to the atm layer. j4 urxsoc o utopia receive start of cell signal. active high asserted by the MT90223 when rxdata contains the first valid word (byte) of a cell. k3 urxclk i utopia receive clock . this signal is the clock driven from the atm layer to the phy layer. data changes after the rising edge of this signal. k2 urxenb i utopia receive data enable. active low signal asserted by the atm layer device to indicate that urxdata[15:0] ([7:0]) and urxsoc will be sampled at the end of the next cycle. in multiple phy configurations, urxenb is used to tri-state urxdata and urxsoc MT90223 outputs. in this case, urxdata and urxsoc would be enabled only in cycles following those with urxenb asserted. in utopia l1, urxenb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer. j3 urxclav o utopia receive cell available signal. for cell-level flow control in a mphy environment, urxclav is an active high tri-stateable signal from the MT90223 to atm layer device.
mt90222/3/4 data sheet 21 zarlink semiconductor inc. l1, l2, l4, l3, k1 urxaddr [4:0] i receive address . five bit wide address bus driven from the atm to phy device to select the appropriate phy address. urxaddr[4] is the msb. receiver static memory interface signals b7,a7,d8,c8, b8,d9,c9,b9 sr_d [7:0] i/o static memory data bus . data bus to exchange data between the MT90223 and the external static memory. sr_d[7:0] has internal weak pull-downs. a9,c10,b10, a10,c11,d11,b1 1,a11,c12,d12, b12,a12,c13,b1 3,a14,b14,c14, a15,b15 sr_a [18:0] o static memory address bus . address bus on the external static memory. d15 sr_we o static memory read/not write . if low, data is written from the MT90223 to the memory. if high, data is read from the memory to the MT90223. a16,b16 sr_cs_1, 0 o static memory chip select signal. active low. processor interface signals ae8,ad8,af7,a e7,ad7,ac7,af 6,ad6,af5,ae5, ad5,ae4,af3,a d4,ae3,af2 up_d [15:0] i/o processor data bus . data bus to exchange data between the MT90223 and a local processor. ae12,ac12, af11,ae11, ac11,ad11, af10,ae10, ad10,af9, ae9,ad9 up_a [11:0] i processor address bus . used to select the internal registers and memory locations of the MT90223. af12 up_r/w or up_wr i processor read/not write. motorola mode. this is an input signal. if low, data is written from the processor to the MT90223. if high, data is read from the MT90223 to the processor. processor not write (intel mode). this is an input signal, active low. if low, data is written from the processor to the MT90223. ad13 up_oe or up_rd i output enable (motorola mode). this is an input signal. this signal should be tied to gnd for motorola timing mode. processor read (intel mode). this is an input signal, active low. if low, data is read from the MT90223. ae13 up_cs i chip select . this is an active low input signal. if this signal is high, the MT90223 ignores all other signals on its processor bus. if this signal is low, the MT90223 accepts the signals on its processor bus. ac9 up_irq o processor interrupt request . open drain signal. if this signal is low, the MT90223 signals to the processor that an interrupt condition is pending inside the MT90223. MT90223 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 22 zarlink semiconductor inc. tdm interface signals r23 u25 w25 y23 ac26 ae21 ae19 ad17 dsto [14] [12] [10] [8] [6] [4] [2] [0] o serial tdm data output . serial stream which contains transmit data. the output is set to high impedance for unused time slots and if the link is not used. it is aligned with txckio and txsyncio. m26 l24 j23 g25 e26 a25 a22 b20 dsti [14] [12] [10] [8] [6] [4] [2] [0] i serial tdm data input . serial stream which contains receive data. it is aligned with rxcki and rxsynci. these pins have internal weak pull-downs. t26 u24 w24 aa26 ac25 af21 af19 af17 txckio [14] [12] [10] [8] [6] [4] [2] [0 i/o tdm interface transmit clock. this pin is an input or an output as selected by the tdm tx link control registers. the txck source is software selectable and can be either one of the eight rxck or one of the four refck signals when defined as output. when defined as input, the proper clock signal is provided to the input pin. the clock polarity is determined by the tdm tx link control registers. these pins have internal weak pull-downs. t25, v25, w23, aa24, ad26, ad20, ad18, ad16 txsyncio [14] [12] [10] [8] [6] [4] [2] [0] i/o transmit line frame pulse . this pin is an input or an output as selected by the tdm tx link control registers. it is the frame reference (typically 8 khz) used as transmit synchronization for the tdm system interface. when an output, the txsync is generated from the txck signal and is independent from other txsync signals. two major modes are available: generic and st-bus: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32/64/128 channel frame of the st-bus interface at dsti and dsto lines. 2. for generic tdm interfaces, it can be programmed to generate or receive either a positive or negative pulse polarity that mark s the first bit of the tdm system interface. these pins have internal weak pull-downs. m25 k26 j24 g23 d26 b24 c21 a20 rxsynci [14] [12] [10] [8] [6] [4] [2] [0] i receive line frame pulse . it is the frame reference (typically 8 khz) used as receive synchronization for the tdm system interface. two major modes are available: generic and st-bus: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32/64/128 channel frame of the st-bus interface at dsti and dsto lines. 2. for generic tdm interfaces, it can be programmed to accept either a positive or negative pulse polarity that marks the first bit of the tdm system interface. these pins have internal weak pull-downs. n24 l25 j25 g26 f24 c23 b22 c20 rxcki [14] [12] [10] [8] [6] [4] [2] [0] i tdm interface receive clock. this input line represents the clock for the receive serial tdm data. the expected frequency value to be received at this input clock is defined by the user through the rx link tdm control register. these pins have internal weak pull-downs. MT90223 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 23 zarlink semiconductor inc. ab2,ab1 pllref [1:0] o output reference to an external pll . aa3,aa4, aa1,y3 refck [3:0] i input reference clock inputs 3 to 0. receive the de-jittered transmit clock reference to be internally routed to the txckio transmit clocks. these pins have internal weak pull-downs. tdm ring signals d16 txringclk o tdm ring tx clock. clock output signal used to align the txringsync and txringdata. should be connected to the rxringclk input of the next MT90223 device in the ring. this output is in high z state if the tdm ring is not used. not 5 v tolerant. a17 txringsync o tdm ring tx sync. synchronization output signal used to retrieve data and control from the bytes on txringdata. should be connected to the rxringsync input of the next MT90223 device in the ring. this output is in high z state if the tdm ring is not used. not 5 v tolerant. b17,c17,a18,b1 8,d18,c18,a19, b19 txringdata [7:0] o tdm ring tx data[7:0]. data bus connecting the tx tdm ring port to the rx tdm ring port. should be connected to the rxringdata inputs of the next MT90223 device in the ring. these output are in high z state if the tdm ring is not used. not 5 v tolerant. af13 rxringclk i tdm ring rx clock. clock input signal used to align the rxringsync and rxringdata. should be connected to the txringclk input of the previous MT90223 device in the ring. there is an internal weak pull-down on this input. not 5 v tolerant. af14 rxringsync i tdm ring rx sync. synchronization input signal used to retrieve data and control from the bytes on rxringdata. should be connected to the txringsync output of the previous MT90223 device in the ring. there is an internal weak pull-down on this input. not 5 v tolerant. ac16,ae16, af16,ac15, ae15,af15, ad14,ae14 rxringdata [7:0] i tdm ring rx data[7:0]. data bus connecting the rx tdm ring port to the tx tdm ring port. should be connected to the txringdata inputs of the previous MT90223 device in the ring. there are internal weak pull-downs on these inputs. not 5 v tolerant. system signals ac1 clk i system clock (50 mhz nominal) . in the MT90223, this clock is used for all internal operations of the device. c19 latchclk i counter latch clock. the clock present at this input can be divided internally to produce the latch signal for the internal counters. refer to the counter transfer command register for more details. this pin has an internal pull-down. a4 reset i system reset. this is an active low input signal. it causes the device to enter the initial state. the clk signal must be active to reset the internal registers. d7 tck i jtag test clock. tck should be pulled down if not used. a5 tms i jtag test mode select . tms is sampled on the rising edge of tck. b6 tdi i jtag test data input . this pin has an internal weak pull-down. c6 tdo o jtag test data output . note: tdo is tristated by trst pin. b5 trst i jtag test reset (active low). should be asserted low on power-up and during reset. must be high for jtag boundary-scan operation. this pin has an internal weak pull-down. ad1 test1 i test1. must be tied low d19 test2 o test2 . must be left not connected (nc). MT90223 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 24 zarlink semiconductor inc. c7 test3 i test3 . must be pulled up to v3.3 for normal operation. not 5 v tolerant. b4 test4 o test4 . must be left not connected (nc) power signals e2,h1,j1,m3, p2,t3,y2,ab3,a e6,af8, ad12,ad15, ac19,ad25, aa25,v26, n25,h26,f26,a2 3,d20,c16,a13, a8,c5 vdd5 s 5 volt supply pin . connect to a 5 volt supply when interfacing to 5 volt signals, otherwise, connect to a 3.3 volt supply. aa23,ab04, ac06,ac13, ac17,ac22, d6,d10,d14, d22,e23,f4, k23,n4,p23, u4 v3.3 s 3.3 volt supply pin for i/o pins. connect to a 3.3 volt supply. d13,d17,n23,u2 3,ac10, ac14,k4,p4 v2.5 s 2.5 volt supply for core. connect to a 2.5 volt power supply. ab23,ac4, ac5,ac23, ad3,ad24, ae2,ae25,b2,b2 5,c3,c24, d4,d5,d23,e4,l 11,l12,l13, l14,l15,l16, m11,m12,m13,m 14,m15,m16,n11 ,n12,n13,n14,n 15,n16,p11,p12, p13,p14,p15,p1 6, r11,r12,r13,r1 4,r15,r16,t11,t 12,t13, t14,t15,t16 vss s ground. MT90223 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 25 zarlink semiconductor inc. b1,j2,m1,y1, aa2,ac2,ad2,a e1,ac3,af4,ac 8,ae17, ac20,ad21, af22,af23, ad22,ae23, af24,ae24, af25,ad23, ae26,r24, l23,e25,c25, b26,d24,c15,a6 ,a3,c4, b3,a2, p24, t23, v24,y26, ab26, ac24, ae20,ac18 p26, m24, k24, h23, f25, c26, b23, b21 n26, l26, j26, h24, f23, d25, c22, a21, p25, m23, k25, h25, g24, e24, a24, d21 nc i not connected. r26, t24, v23, y25, ab25, ae22, af20, ae18, r25, u26, w26, y24, ab24, ac21, ad19, af18 pd pull-down. connect to vss via a high va lue resistor, e.g., 10 k ohm. MT90223 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 26 zarlink semiconductor inc. mt90224 pin description pin # name i/o description atm input port signals (utopia transmit interface) u2,u1,t4,t2, t1,r3,r4,r2,r1, p3,p1,n1,n2,n3, m2,m4 utxdata [15:0] i utopia transmit data bus. 16 (or 8) bit wide data driven from atm layer device to mt90224. bit 15 (or 7) is the msb. all arriving data between the last word (byte) of the previous cell and the first word (byte) of the following cell (indicated by the soc signal) is ignored. utxdata[15:8] have internal weak pull-downs. u3 utxpar i utopia transmit parity. odd (or even) parity bit generated by the atm layer. the parity bit is sampled on the rising edge of utxclk. utxpar has an internal weak pull-down. v1 utxsoc i utopia transmit start of cell signal. active high signal asserted by the atm layer device when txdata[15:0] ([7:0]) contains the first valid word (byte) of the cell. after this signal is high, the following 26 word (52 bytes) should contain valid data. the mt90224 waits for another txsoc and txenb signal after reading a complete cell. an external pull-down (4.7 k) is strongly recommended. v4 utxclk i utopia transmit clock. transfer clock from the atm layer device to the mt90224 which synchronizes data transfers on txdata[15:0] ([7:0]). this signal is the clock of the incoming data. data is sampled on the rising edge of this signal..for 8-bit utopia mode the maximum supported clock is 52 mhz and for 16-bit utopia mode maximum supported clock is 33 mhz. v3 utxenb i utopia transmit data enable. active low signal asserted by the atm layer device during cycles when txdata contains valid cell data. v2 utxclav o utopia transmit cell available signal. for cell-level flow control in a mphy environment, txclav is an active high tri-stateable signal from the mt90224 to the atm layer device. y4,w3,w4, w2,w1 utxaddr [4:0] i transmit address . five bit wide address bus driven by the atm layer device to poll and select the appropriate phy address. txaddr[4] is the msb. atm output port signals (utopia receive interface) h3,h4,g1,g2,g3, g4,f1,f2, f3,e1,e3,d1, d2,c1,d3,c2 urxdata [15:0] o utopia receive data bus. 16 (or 8) bit wide data driven from mt90224 to atm layer device. rxdata[15] ([7]) is the msb. to support multiple phy configurations, rxdata is driven only when rxenb and port is selected. it is tri-stated otherwise. h2 urxpar o utopia receive parity. odd (or even) parity bit generated by the mt90224 to the atm layer. j4 urxsoc o utopia receive start of cell signal. active high asserted by the mt90224 when rxdata contains the first valid word (byte) of a cell. k3 urxclk i utopia receive clock . this signal is the clock driven from the atm layer to the phy layer. data changes after the rising edge of this signal. k2 urxenb i utopia receive data enable. active low signal asserted by the atm layer device to indicate that urxdata[15:0] ([7:0]) and urxsoc will be sampled at the end of the next cycle. in multiple phy configurations, urxenb is used to tri-state urxdata and urxsoc mt90224 outputs. in this case, urxdata and urxsoc would be enabled only in cycles following those with urxenb asserted. in utopia l1, urxenb must not be tied low and must transition from high (disabled) to low (enabled) to indicate the beginning of data transfer. j3 urxclav o utopia receive cell available signal. for cell-level flow control in a mphy environment, urxclav is an active high tri-stateable signal from the mt90224 to atm layer device. l1, l2, l4, l3, k1 urxaddr [4:0] i receive address . five bit wide address bus driven from the atm to phy device to select the appropriate phy address. urxaddr[4] is the msb.
mt90222/3/4 data sheet 27 zarlink semiconductor inc. receiver static memory interface signals b7,a7,d8,c8, b8,d9,c9,b9 sr_d [7:0] i/o static memory data bus . data bus to exchange data between the mt90224 and the external static memory. sr_d[7:0] has internal weak pull-downs. a9,c10,b10, a10,c11,d11,b11 ,a11,c12,d12,b1 2,a12,c13,b13,a 14,b14,c14,a15, b15 sr_a [18:0] o static memory address bus . address bus on the external static memory. d15 sr_we o static memory read/not write . if low, data is written from the mt90224 to the memory. if high, data is read from the memory to the mt90224. a16,b16 sr_cs_1, 0 o static memory chip select signal. ac tive low. processor interface signals ae8,ad8,af7,ae 7,ad7,ac7,af6, ad6, af5,ae5,ad5,ae 4,af3,ad4,ae3, af2 up_d [15:0] i/o processor data bus . data bus to exchange data between the mt90224 and a local processor. ae12,ac12, af11,ae11, ac11,ad11, af10,ae10, ad10,af9, ae9,ad9 up_a [11:0] i processor address bus . used to select the internal registers and memory locations of the mt90224. af12 up_r/w or up_wr i processor read/not write. motorola mode. this is an input signal. if low, data is written from the processor to the mt90224. if high, data is read from the mt90224 to the processor. processor not write (intel mode). this is an input signal, active low. if low, data is written from the processor to the mt90224. ad13 up_oe or up_rd i output enable (motorola mode). this is an input signal. this signal should be tied to gnd for motorola timing mode. processor read (intel mode). this is an input signal, active low. if low, data is read from the mt90224. ae13 up_cs i chip select . this is an active low input signal. if this signal is high, the mt90224 ignores all other signals on its processor bus. if this signal is low, the mt90224 accepts the signals on its processor bus. ac9 up_irq o processor interrupt request . open drain signal. if this signal is low, the mt90224 signals to the processor that an interrupt condition is pending inside the mt90224. tdm interface signals p24,r23,t23,u2 5,v24,w25,y26,y 23, ab26,ac26, ac24,ae21, ae20,ae19, ac18,ad17 dsto [15:0] o serial tdm data output 15-0 . serial stream which contains transmit data. the output is set to high impedance for unused time slots and if the link is not used. it is aligned with txckio and txsyncio. mt90224 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 28 zarlink semiconductor inc. p26,m26,m24,l2 4,k24,j23, h23,g25,f25,e2 6,c26,a25,b23,a 22,b21,b20 dsti [15:0] i serial tdm data input 15-0 . serial stream which contains receive data. it is aligned with rxcki and rxsynci. these pins have internal weak pull-downs. r26,t26,t24,u24 ,v23,w24,y25,a a26, ab25,ac25, ae22,af21, af20,af19, ae18,af17 txckio [15:0] i/o tdm interface transmit clock 15-0. this pin is an input or an output as selected by the tdm tx link control registers. the txck source is software selectable and can be either one of the sixteen rxck or one of the four refck signals when defined as output. when defined as input, the proper clock signal is provided to the input pin. the clock polarity is determined by the tdm tx link control registers. these pins have internal weak pull-downs. r25,t25,u26,v2 5,w26,w23,y24, aa24, ab24,ad26, ac21,ad20, ad19,ad18, af18,ad16 txsyncio [15:0] i/o transmit line frame pulse 15-0 . this pin is an input or an output as selected by the tdm tx link control registers. it is the frame reference (typically 8 khz) used as transmit synchronization for the tdm system interface. when an output, the txsync is generated from the txck signal and is independent from other txsync signals. two major modes are available: generic and st-bus: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32/64/128 channel frame of the st-bus interface at dsti and dsto lines. 2. for generic tdm interfaces, it can be programmed to generate or receive either a positive or negative pulse polarity that marks the first bit of the tdm system interface. these pins have internal weak pull-downs. n26,m25,l26,k2 6,j26,j24, h24,g23,f23,d2 6,d25,b24,c22,c 21,a21,a20 rxsynci [15:0] i receive line frame pulse 15-0 . it is the frame reference (typically 8 khz) used as receive synchronization for the tdm system interface. two major modes are available: generic and st-bus: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32/64/128 channel frame of the st-bus interface at dsti and dsto lines. 2. for generic tdm interfaces, it can be programmed to accept either a positive or negative pulse polarity that marks the first bit of the tdm system interface. these pins have internal weak pull-downs. p25,n24,m23,l2 5,k25,j25, h25,g26,g24,f2 4,e24,c23,a24,b 22,d21,c20 rxcki [15:0] i tdm interface receive clock 15-0. this input line represents the clock for the receive serial tdm data. the expected frequency value to be received at this input clock is defined by the user through the rx link tdm control register. these pins have internal weak pull-downs. ab2,ab1 pllref [1:0] o output reference to an external pll . aa3,aa4, aa1,y3 refck [3:0] i input reference clock inputs 3 to 0. receive the de-jittered transmit clock reference to be internally routed to the txckio transmit clocks. these pins have internal weak pull-downs. tdm ring signals d16 txringclk o tdm ring tx clock. clock output signal used to align the txringsync and txringdata. should be connected to the rxringclk input of the next mt90224 device in the ring. this output is in high z state if the tdm ring is not used. not 5 v tolerant. a17 txringsync o tdm ring tx sync. synchronization output signal used to retrieve data and control from the bytes on txringdata. should be connected to the rxringsync input of the next mt90224 device in the ring. this output is in high z state if the tdm ring is not used. not 5 v tolerant. b17,c17,a18,b1 8,d18,c18,a19,b 19 txringdata [7:0] o tdm ring tx data[7:0]. data bus connecting the tx tdm ring port to the rx tdm ring port. should be connected to the rxringdata inputs of the next mt90224 device in the ring. these output are in high z state if the tdm ring is not used. not 5 v tolerant. mt90224 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 29 zarlink semiconductor inc. af13 rxringclk i tdm ring rx clock. clock input signal used to align the rxringsync and rxringdata. should be connected to the txringclk input of the previous mt90224 device in the ring. there is an internal weak pull-down on this input. not 5 v tolerant. af14 rxringsync i tdm ring rx sync. synchronization input signal used to retrieve data and control from the bytes on rxringdata. should be connected to the txringsync output of the previous mt90224 device in the ring. there is an internal weak pull-down on this input. not 5 v tolerant. ac16,ae16, af16,ac15, ae15,af15, ad14,ae14 rxringdata [7:0] i tdm ring rx data[7:0]. data bus connecting the rx tdm ring port to the tx tdm ring port. should be connected to the txringdata inputs of the previous mt90224 device in the ring. there are internal weak pull-downs on these inputs. not 5 v tolerant. system signals ac1 clk i system clock (50 mhz nominal) . in the mt90224, this clock is used for all internal operations of the device. c19 latchclk i counter latch clock. the clock present at this input can be divided internally to produce the latch signal for the internal counters. refer to the counter transfer command register for more details. this pin has an internal pull-down. a4 reset i system reset. this is an active low input signal. it causes the device to enter the initial state. the clk signal must be active to reset the internal registers. d7 tck i jtag test clock. tck should be pulled down if not used. a5 tms i jtag test mode select . tms is sampled on the rising edge of tck. b6 tdi i jtag test data input . this pin has an internal weak pull-down. c6 tdo o jtag test data output . note: tdo is tristated by trst pin. b5 trst i jtag test reset (active low). should be asserted low on power-up and during reset. must be high for jtag boundary-scan operation. this pin has an internal weak pull-down. ad1 test1 i test1. must be tied low d19 test2 o test2 . must be left not connected (nc). c7 test3 i test3 . must be pulled up to v3.3 for normal operation. not 5 v tolerant. b4 test4 o test4 . must be left not connected (nc) power signals e2,h1,j1,m3, p2,t3,y2,ab3,ae 6,af8, ad12,ad15, ac19,ad25, aa25,v26, n25,h26,f26,a2 3,d20,c16,a13,a 8,c5 vdd5 s 5 volt supply pin . connect to a 5 volt supply when interfacing to 5 volt signals, otherwise, connect to a 3.3 volt supply. aa23,ab04, ac06,ac13, ac17,ac22, d6,d10,d14, d22,e23,f4, k23,n4,p23, u4 v3.3 s 3.3 volt supply pin for i/o pins. connect to a 3.3 volt supply. mt90224 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 30 zarlink semiconductor inc. 1.0 device architecture the mt90222/3/4, supported by software, implements the atm forum inverse multiplexing for asynchronous transfer mode (ima) specification. actions are impl emented by the mt90222/3/4 and decisions are made by the software. this approach minimizes the impact of an y changes that might occur in the specification. the mt90222/3/4 supports the following two major modes of operation: ? the ima mode (as defined by the atm forum ima specification), both version 1.0 and 1.1 ? the transmission convergence (tc) mode. up to eight ima groups can be implemented (4 groups - 0, 1,2,3 for mt90222) any of th e available serial (tdm) interfaces can be assigned dynamically to any of these ima groups. a different utopia phy address is assigned to each of the ima groups. the tc mode is used to transfer the cells from the utopia interface to a serial (tdm) port without any overhead. up to 16 utopia phy addresses can be supported in tc mode (one per serial port). the mt90222/3/4 also supports a mixed mode where the tdm interfaces not assigned to an ima group can be used in tc mode. d13,d17,n23,u2 3,ac10, ac14,k4,p4 v2.5 s 2.5 volt supply for core. connect to a 2.5 volt power supply. ab23,ac4, ac5,ac23, ad3,ad24, ae2,ae25,b2,b2 5,c3,c24, d4,d5,d23,e4,l1 1,l12,l13, l14,l15,l16, m11,m12,m13,m 14,m15,m16,n11, n12,n13,n14,n1 5,n16,p11,p12,p 13,p14,p15,p16, r11,r12,r13,r1 4,r15,r16,t11,t 12,t13, t14,t15,t16 vss s ground. b1,j2,m1,y1, aa2,ac2,ad2,ae 1,ac3,af4,ac8, ae17, ac20,ad21, af22,af23, ad22,ae23, af24,ae24, af25,ad23, ae26,r24, l23,e25,c25, b26,d24,c15,a6, a3,c4, b3,a2 nc i not connected. mt90224 pin description (continued) pin # name i/o description
mt90222/3/4 data sheet 31 zarlink semiconductor inc. the ima implementation is divided into hardware a nd software functions. the mt90222/3/4 implements the hardware functions. the software functions are implemen ted by the user or zarlink ima core. the hardware and software functions are described below. notice that a numbe r of mt90222/3/4 functions are included to assist in the collection of statistical information. this information supports the mib implementation. 1.1 software functions for the mt90222/3/4 to comply with the ima specificat ion, the following functi ons must be implemented by software: ? the transmit and receive link state machines (lsm) ? the ima group state machines (gsm) ? the ima group traffic state machines (gtsm) ? the operations and maintenance (oam) functions 1.1.1 link state machines the software implemented transmit and receive lsms are independent (i.e., each link has its own lsm). lsms rely on various events from: the mt90222/3/4 interface, such as cell errors, excessive delay between-links, etc.; or, from the t1/e1/j1/dsl framer, such as loss of signal (los), loss of frame (lof), remote alarm indication (rai) etc. on-chip registers are used to generate the icp cells that communicate t he lsm states at the far end (fe). 1.1.2 ima group state machines the ima gsms and group traffic state machines (gtsm) mu st be implemented in software. one of each state machine should be implemented for each ima group. on-chip registers are used to generate the icp cell s that communicate the va rious states to the fe. 1.1.3 link addition, removal or restoration the addition, removal or restoration of a link is controlled by software using the various control registers in the mt90222/3/4 and in the t1/e1j1/dsl framers. de cisions are based on the mt90222/3/4 and typically t1/e1/j1/dsl framer status registers. 1.1.4 interrupts the mt90222/3/4 provides numerous regi sters and counters to implement a po lling and/or interrupt mechanism for tracking link and ima group status. this traffic in and ou t information is used by the management information base (mib) for each ima group. 1.1.5 signalling and rate adjustment the microprocessor controls the opera tion of the serial links by provid ing handshaking between the far end (fe) and near end (ne) including such functions as signaling and loopback controls. rate adjustment is controlled by: ? adding or removing one or more serial links ? providing feedback to the atm network for adjusting the atm traffic.
mt90222/3/4 data sheet 32 zarlink semiconductor inc. 1.1.6 performance monitoring software implements most of the performance monitori ng. the mt90222/3/4 provides status information for: ? the cell delineation block and ima frame state machine ? the number of icp violations ? the total number of cells ? the total number of user cells ? the number of idle or discarded cells. it also provides the content for received icp cells that contain some changes. the external t1/e1/j1/dsl framers provide the low level status of the link. the software integrates and responds to the various events. 1.2 hardware functions the mt90222/3/4 circuitry implements the following functions: ? utopia l1 and l2 compatible interface (8- bit mode wide bus supported with utopia clock of up to 52 mhz and 16- bit wide with utopia clock of up to 33 mhz) ? verification of the incoming hec (optional) ? generation of a new hec byte ? transmit scheduler ? generation of the tx ima data cell rate (idcr) clock ? generation and insertion of icp cells, fi ller cells and stuff cells in ima mode ? generation of idle cells in tc mode (from on-chip copies of the cell) ? flexible serial link (tdm) formatting of the outgoing bytes ? retrieval of atm cells from the incoming flexible tdm format ? cell delineation ? retrieval and processing of icp cells ? synchronization of the ima frame ? management of the internal re-sequencer rx links (when active) ? extraction of the rx idcr ? verification of the delays between links ? re-sequencing of atm cells using external static ram ? various performance monitoring counters ? 16-bit microprocessor interface (adaptable to intel or motorola interfaces) the mt90222/3/4 can be separated into four major ind ependent blocks and five support blocks.the four major independent blocks are: ? the atm transmit path ? the atm receive path ? the tdm interface ? the utopia interface
mt90222/3/4 data sheet 33 zarlink semiconductor inc. the five support blocks are: ? the counter block ? the interrupt block ? the microprocessor interface block ? the cell preprocessor block ? the tdm ring block 2.0 the atm transmit path the transmit path corresponds to a cell flow from the atm layer towards the phy layer. the atm cell path on the transmit side starts at the utopia l2 or l1 interface. once atm cells are received at the utopia port, the device transfers these cells to the transmit block. the mt90222/3/4 provides atm cell mapping and transmission convergence blocks to transport atm cells over a maximum of sixteen flexible serial interface ports. these se rial interface ports communica te with most off-the-shelf t1/e1/j1 framers, xdsl modems or other low speed link devices. each of these serial links can be assi gned to either an ima group or to a tc link. a single serial link cannot be assigned to more than one ima group. the mt90222 suppor ts up to 4 serial links, while the MT90223 supports up to 8 serial links and the mt90224 supports up to 16 serial links. the functional block diagram at figure 5 illus trates the transmit f unction of the mt90224. 2.1 cell in control in general terms, the mt90222/3/4 transmit input port has the following properties: ? cell level handshaking is compatible with the atm forum utopia l1 and l2 specification ? behaves like a utopia compatible mphy device or single phy device ? each port can be enabled or disabled independently ? parity (odd or even) can be checked ? optionally verifies and then generates the hec for incoming cells ? includes the atm forum polynomial when generati ng the hec (default option that can be disabled) ? either passes or removes incoming idle cells ? either passes or removes incoming unassigned cells ? provides a counter per utopia port for the total number of idle/unassigned/filler cells with a valid hec or optionally the total number of user cells (24 bits/16 bit latched) ? provides a counter per utopia port for the total num ber of cells with wrong incoming hec (24 bits/16 bit latched) ? provides a counter per utopia port for the tota l number of cells handled (24 bits/16 bit latched) ? provides counters for parity errors the input port can be enabled to remove (filter) unassigned or idle cells. if unassigned or idle cell filtering is enabled, the device checks for and discards unassigned or idle cells. this function is programmed in the utopia input control (0x0052) register. section 5.0 describes the utopia interface in more detail.
mt90222/3/4 data sheet 34 zarlink semiconductor inc. figure 5 - mt90224 functional block diagram -transmitter in ima mode 2.2 the atm transmission convergence the transmit convergence (tc) function is common for both the ima and tc modes. it integrates the circuitry to support atm cell payload scrambling, he c generation and the generation of idle/filler /icp cells for use with the t1/e1/j1 or dsl trunks. each of the avail able atm tc circuits can use the polynomial x 43 + 1 to scramble the atm cell payload field. the mt90222/3/4 atm cell payload scrambling function can be disabled. the itu i.432 polynomial x 8 + x 2 + x + 1 is used to generate the hec fiel d of the atm cell. by default, the atm forum polynomial x 6 + x 4 + x 2 + 1 is added to the calculated hec oc tet. the addition of the atm forum polynomial can be disabled. the resulting calculation is then writt en on the hec field and the atm cell is ready (i.e., complies with the ima transmit protocol) for transmission over the flexible tdm interface. in cases where the tc block requests a cell to be transf erred to any of the serial interfaces and the tx utopia fifo has no cell ready for transmission, then the tc block will automatically send an idle cell (in tc mode) or a filler cell (in ima mode) to the line. the default values for the idle and the filler cells comply with the atm ima atm in cell in cell ram fifo link 0 p/s p/s p/s link 0 serial streams link 1 transmitter utopia l2 filler cell idle cell icp cell group 0 icp cell group 1 icp cell group 7 next icp cell group 0 next icp cell group 1 next icp cell group 7 icp cell mod. and cell scrambling icp cell mod. and cell scrambling icp cell mod. and cell scrambling link 15 icp cell handler from idcr generator micro i/f (see note 1) fifo link 1 (see note 1) fifo link 15 (see note 1) icp cell buffer ram tx utopia fifo group 7 tx utopia fifo group 0 round robin scheduler and fifo selection and adaptive shaper (1 of 8) idcr generator (1 of 8) transmitter reference link timing to cell_in_control note 1: this fifo is the tx utopia fifo when the link is configured in non-ima mode and it is the tx link fifo when it is configured in ima mode interface control tdm ring control to rx block from tdm ring note 2: in mt90222 groups 0,1,2,3 should be used.
mt90222/3/4 data sheet 35 zarlink semiconductor inc. specification and are pre-loaded in th e mt90222/3/4 following a reset. the tx cell ram control (0x0080) register can be used to re-initialize the tx cell ram. 2.2.1 tx cell ram and tx fifo length the internal tx cell ram can hold up to 128 cells. the following 10 cells are reserved for mt90222/3/4 operation: ? one icp cell for each ima group for a total of eight cells ? one common filler cell used in ima mode ? one idle cell used in tc mode the remaining 118 cells can be assigned to any of the 40 tx fifos. the tx fifos are divided into 24 tx utopia fifos and 16 tx link fifos. the mt90222/3/4 implement s one tx utopia fifo for each link when used in tc mode and one for each ima group, totalling up to 24 tx ut opia fifos. each tx utopia fifo is associated with one tx utopia address. please refer to section 5.0 "utopia interface operation" for more details. in addition, for each link to be used in ima mode, an internal tx link fifo is utilized. these tx link fifos hold the cell streams that are to be sent on each tx serial port. there is a total of 16 tx link fifos and their size is programmed on a per group basis using the tx ima control (0x0321-0x0324) register. when a link is used in tc mode, its corresponding tx link fifo is disabl ed and the tx link utopia fifo is used. the mt90222 and MT90223 support a subset of the 16 links an d only the registers corresp onding to available links are meaningful. tx ima utopia fifo lengt h definition (0x0093-0x0096) registers are used to set the size of the ima fifo. a maximum of 6 cells can be assigned to any single fifo. the size of unused tx ima utopia fifos should be set to zero. the recommended size for the ima group tx utopia fifo is 2. in ima mode, the atm user cells are first placed in the tx ima utopia fifo and then transferred, by the internal round robin scheduler, to the proper tx link fifo. the tx ima control (0x0321-0x0324 ) registers are used to set the size of the internal tx link fifo for a link in ima mode. an upper and lower level limit must be set for the internal tx link fifo. the recommended upper limit value for the internal tx li nk fifo is five and the recommended lower limit is one when operating in itc clocking mode. when operating in ctc mode, the recommended upper limit value for the internal tx link fifo is six and the recommended lower limit is one. in the case where ctc mode is used and when the icp cells on all the links are sent with the same icp cell offset and when carrying a cbr-type traffic, an upper value of 7 may be required. in tc mode, the atm user cells are queued in the tx link utopia fifo (0x008b - 0x0092) until sent over the serial link. 2.3 parallel to serial tdm interface atm cell octet byte alignment conforms to itu g.804 recommendations for t1 or e1 framer parallel to serial format conversion. the tdm tx link control register (0x0600-0x060f) and tdm rx link control register (0x0700-0x070f) registers are used to select the serial mode of operation. additionally, the serial links can operate at rates up to 2.5 mb/s individually, or up to 5.0 mb/s when paired or 10 mb /s when grouped in fours. refer to description of the tdm interface for more details.
mt90222/3/4 data sheet 36 zarlink semiconductor inc. 2.4 atm transmit path in ima mode the mt90222/3/4 supports up to eight independent ima groups. each of the available serial links can be assigned to any one of these ima groups. a serial link cannot be assi gned to more than one ima group. refer to figure 5 for a functional block diagram of the transmitter. the ima transmitter splits the incoming stream into n sub-streams, where 1 n (maximum available serial links). each sub-stream is passed to a separate line interf ace device that transmits the cells on a physical link. the physical line rate is 1.544 mbps (t1), 2.048 mbps (e1) or any serial rate up to 2.5 mb/s (serial mode). the transmitter inserts icp cells in the va rious outgoing streams according to th e ima specification. the icp cells are inserted every m atm cells on each link and is the task of the scheduler. 2.4.1 ima frame length (m) the ima frame length (value of m) can be 256, 128, 64, or 32. the value of m for each ima group is set by the tx ima group fifo length definition (0x0093-0x0096) registers. m is fixed once an ima group is setup and should remain unchanged as long as that group is operational. 2.4.2 position of the icp cell in the ima frame the tx icp cell offset (0x0310-0x0317) registers control the position of t he icp cell in the ima frame for each link. this parameter should remain unchang ed as long as that gr oup is operational. 2.4.3 transmit clock operation the mt90222/3/4 supports both the common transmit cl ock (ctc) and independent transmit clock (itc) modes of operation. the desired mode is specified by writing to the tx group control mode (0x0300-0x0307) register. a reference link must be specified in the tx group control mode (0x0300-0x0307) register. the mt90222/3/4 introduces a stuff cell on the reference link every 2048 cells and determines the appropriate time to insert a stuff cell on the remaining group links. see paragr aph 2.4.4, stuff cell rate, for more details. the clocking mode and reference link are fixed once an ima group is set up and should remain unchanged as long as that group is operational. the refe rence link should not change unless pr oblems are reported with the link. 2.4.4 stuff cell rate the stuff event algorithm differs between ctc and itc modes. in ctc mode, the stuff event is typically fixed and appears in the same ima frame on all ima group links. in itc mode, the stuff event is determined using an adaptive algorithm that relates the level of the internal tx link fifo to that of the tx link fifo of the reference link. the mt90222/3/4 implements 2 different stuffing algorithms: a fixed stuffing rate and an adaptive stuffing rate. the stuffing events do not happen more frequentl y than once every five ima frames. tx group control mode (0x0300-0x0307) register bit 4 selects either the adaptive or fixed algorithm. bit 5 determines the timing mode declared in the icp cell. there are three possible combinations: ? ctc mode with internal fixed algorithm ? ctc mode with internal adaptive algorithm ? itc mode with internal adaptive algorithm
mt90222/3/4 data sheet 37 zarlink semiconductor inc. in ctc mode, when using the fixed algorithm, the stuff event is periodic and will appear in the same ima frame, once every 2048 cells, on each link that is part of the ima group. in ctc mode, when using the adaptive algorithm, the st uff event will occur at an average rate of once every 2048 cells on each link and may not occur in the same ima frame on all the links. the reference link has one stuff event every 2048 cells. in itc mode, the stuff event is determin ed using the adaptive algorithm that rela tes the level of the internal tx link fifo with that of the tx link fifo of the reference link. the reference link has one stuff event every 2048 cells. the state of bits 7 and 15 in the tx ima control (0x0321-0x0324) register determines whet her a stuff indication is generated in the first or first four frames preceding a stuff event. 2.4.5 ima data cell rate the mt90222/3/4 computes the internal tx ima data cell rate (idcr) for each ima group. the cell rate for the ima group reference link, specified in the tx group control mode (0x0300-0x0307) register, is integrated over a programmable period of time. the preferred integration period is progra mmed in the tx idcr integration register and the value is indicated in table 1. table 1 - idcr integration register value alternately, the integratio n period can be determined us ing the following equation: numberofcells(perperiod) = [ cellrate(persecond) ] [ integrationperiod(insecond) ] the optimum performance will be reached when selecting an in tegration period which resu lts in a number of cells per integration period which is close to an integer number of cells. as example, for a cell rate equivalent to e1 service (30 timeslots per frame with a frame rate of 8 khz). numberofcells = 94.97 = [30 bytes z 8 khz /(53 bytespercells )] [( 2 20) z 1/(50 mhz )] tdm mode preferred value tx idcr integration register (50 mhz) t1 isdn (23 channels) 2 17 clocks t1 (24 channels) 2 19 clocks e1(30 channels) 2 20 clocks
mt90222/3/4 data sheet 38 zarlink semiconductor inc. 2.4.6 ima controller (roundrobin scheduler) the ima controller produces the cell stream to be sent to the tdm blocks using the following four cell types: ? data cells received from the utopia port (user cells) ? filler cells ? ima icp cells with link status information ?stuff cells at an idcr clock tick, the roundrobin scheduler inserts either an icp cell, a user cell or a filler cell into the tx link fifo of the next link of the ima group, based on ascending link id numbers. an icp cell is inserted every m cells and a stuff event is inserted wh en indicated by the stuffing algorithm. if it is not time for an icp cell and if the traffic is not enab led for the link, then a filler cell is in serted in the tx link fifo. if the traffic is enabled and there is a user cell in the tx ima utopia fifo, then the user cell is transferred from the tx ima utopia fifo to the tx link fifo. if there is no user cell in the tx ima utopia fifo, then a filler cell is inserted in the tx link fifo. byte description control source 1-5 icp cell header content of header is under s/w control. the hec is calculated by h/w. 6 oam label s/w control 7 cell id, link id hardware control. the link id is programmed by s/w via other registers. 8 ima frame sequence hardware control 9 icp cell offset h/w control (program med by s/w through other registers) 10 link stuff indication h/w control (pr ogrammed by s/w through other registers) 11 status change indic. h/w control 12 ima id s/w control 13 group status and control s/w control except for value of m 14 sync. info. h/w control (programme d by s/w through other registers) 15 test control s/w control 16 tx test pattern s/w control 17 rx test pattern s/w control 18-49 link status and control s/w control 50 unused s/w control 51 end-to-end channel s/w control 52-53 crc error control h/w calculation table 2 - icp cell description
mt90222/3/4 data sheet 39 zarlink semiconductor inc. 2.4.7 icp cell generator once per ima frame, an icp cell is transmitted on each link of the ima group. the content of the icp cell is controlled both by mt90222/3/4 and software. the software cont ent of the icp cell bytes is stored in buffer ram. a copy of the icp cell for each group is kept in the internal transmitter cell ram. the icp cell to be transmitted on each link is assembl ed on an as required basis under the control of the internal roundrobin scheduler and icp cell modifier. hardware controls the following bytes of the icp cell: ? byte 5 - the hec is always calculated and inserted by the mt90222/3/4 ? byte 6 - the tx oam label is defined by the software and the value contained in this location is transmitted in all icp cells, stuff cells and filler cells sent on all the links that are part of the corresponding tx ima group ? byte 7 - the tx link id (0x0336 - 0x033d) registers are used to set the link logical id and the cell type is determined by the internal controller on a per link basis ? byte 8 - the frame sequence number is controlled by an internal counter ? byte 9 - the tx icp cell offset (0x0310-0x0317) registers are used to set this value and is inserted on a per link basis ? byte 10 - the link stuff indication is inserted aut omatically and the advance indication option is programmed by the tx ima control (0x0321-0x0324) registers on a per link basis ? byte 11 - the scci is controlled by internal circuitr y. the scci is incremented by one for each transfer of the tx icp cell from the buffer area to the tx cell ram. ? byte 13 - the value of m is programmed through the tx group control mode (0x0300-0x0307) register ? byte 14 - the tx group control mode (0x0300-0x0307) register is used to set the transmit timing information and define the reference link ? bytes 52 and 53 - the calculated crc-10 error control bits are inserted automatically software controls all remaining bytes of the icp cells. it also maintains and updates all bytes that are not directly controlled by the mt90222/3/4. a dedica ted address is reserved for each icp cell byte for each of the eight ima groups. this permits direct access to any of the bytes stored in each of the eight icp cell registers. refer to table 2, icp cell description, for details on the icp cell byte contents. to avoid updating or corrupti on problems, the internal copy of the icp cell cannot be directly accessed. icp cells are prepared in a buffer area (ram inside the mt90222/3/ 4) and transfer commands are issued to copy the content of the icp cell into the internal cell ram area and to start using this new icp cell. the mt90222/3/4 uses a flag (status bit) to indicate that this transfer is underway. changes should not be made to the content of the icp cell in the buffer area until the transfer to the in ternal memory is complete. the status bit is cleared during the transfer and returns to ?1? on completion of the transfer. ima groups are controlled independently. when access to the icp cell of one group is prohib ited, the other icp cell buffer areas ca n still be updated. the tx icp cell handler (0x0086) and tx icp cell interrupt enable (0x0088) registers are used to init iate a transfer and en able an optional interrupt to indicate when the process is complete. the scci field is incremented by one for each trans fer command performed which includes a change in at least one byte of the icp cell. 2.4.8 ima frame programmable interrupt an optional interrupt is provided at the end of an ima fr ame to simplify software implemented changes in the group control and status field. this interrupt can be enabled on an as required and per group basis to implement a frame counter. the tx ima frame indication (0x0087) and tx ima frame interrupt enable (0x0089) registers are used for the end of frame indication and frame interrupt.
mt90222/3/4 data sheet 40 zarlink semiconductor inc. 2.4.9 filler cell definition the content of the filler cell is pre-initialized and confor ms with the ima specification. the oam label in the filler cell is copied from the icp cell, allowing both ima 1.0 and ima 1.1 to run simultaneously on the same device. 2.4.10 tx ima group start-up initialize the tx ima group start-up as follows: (note: the startup procedure below is given indicating the most important steps. a more detailed and complete sequence can be found in the zarlink ima core softwa re). for mt90222 only groups 0, 1, 2 and 3 are used. ? configure the tx tdm port(s) by writing to the tdm tx link control (0x0600-0x060f) registers. ? write the value of m, the timing mode and the reference link number to the tx group control mode (0x0300-0x0307) register corresponding to the ima group number to be initialized. ? write the link id (lid is between 0-31) to tx link id (0x0336-0x033d) registers for each link to be used in the ima group. lid should not be changed when a group is operational. ensure each link that is part of an ima group has a unique lid (note that the mt90222/3/4 does not verify lids). ? write the icp cell offset value to tx icp cell offset (0x0310-0x0317) registers. this value depends on the value of m. typically, the reference link will have a del ay of 0 cells in the ima frame and the icp cell in each other link will be evenly spaced in a multiple of m/n cell s (where m is defined in the ima specification and n is the number of links). the offset value for an operational group should not be changed. ? write to the tx link control (0x0318-0x031f) registers to put the link(s) in ima mode and to enable the transfer of atm user cells when required. 2.4.11 tx link addition the mt90222/3/4 supports software controlled link additi on to an existing ima group. link addition is used to increase the available bandwidth. the tx link control registers (0x0318-0x031f), the tx link id (0x0336-0x033d) and tx icp cell offset (0x0310-0x0317) registers are initialized first with the proper ima group information. the link is assigned to a tx ima group by writing to bits 10:8 or bits 2:0 of the tx link control (0x0318-0x031f) register. before the tx link can be configured in ima mode, the value of 0x108 + group number has to be written in the tx add link control register (0x0333) . the link is then configured in ima mode by writing to the bit 3 or 11 of the tx link control (0x0318-0x031f) register. the tx ima mode status (0x0346) register is monitored to detect when the link is reported in ima mode. tx link control (0x0318-0x031f) register bit 6 or 14 determines when atm user cells can be sent. then the bit 3 of the tx add link control register (0x0333) is written with 0x0100. 2.4.12 tx link deletion there are two reasons to remove a link: the required bandwidth decreases or a link becomes faulty. the mt90222/3/4 supports link deactivation under software control. a link stops transmitting user cells when bit 6 or 14 of the tx link control register (0x0318-0x031f) is set to 0. filler and icp cells will still be sent on the link. the link is removed from an im a group by first setting bit 3 or 11 of the tx link control re gister (0x0318-0x031f) to 1 while keeping the original ima group number. the ima group number can be changed only when the link is in tc mode as reported in the tx ima mode status register (0x0346) . it then can be assigned to another ima group. when removing the last link of a tx ima group, the tx utopia fifo has to be empty. this can easily be done by first disabling the source of atm cells (atm utopia cont roller), then disabling the tx ima utopia port using the utopia input link phy enable (0x0050) or utopia input group phy enable (0x0051) registers while still keeping the "send user cell" bit of the tx link control (0x0318-0x031f) register set to 1. the above procedure can then be applied to assign the link in tc mode.
mt90222/3/4 data sheet 41 zarlink semiconductor inc. when the link is configured in tc mode, idle cells are transmitted. writing to the tdm tx link control (0x0600-0x060f) registers either turns off t he transmitter or rec onfigures the link into another mode. figure 6 - functional block di agram of the transmitter in tc mode (for link[n], 0 n 15) 2.5 atm transmit path in tc mode a maximum of sixteen independent serial interfaces can be configured in tc mode (16 for the mt90224, 8 for the MT90223 and 4 for the mt90222). figure 6 gives a functional block diagram of the transmitter in transmission convergence (tc) mode. atm cells received from the atm port are placed in a tx link utopia fifo, waiting to be transmitted. if the idle/unassigned cell removal option is selected, these cells are dropped. if the tx link utopia fifo is empty, an idle cell is sent to the output link. the content of the id le cell is pre-initialized with the header bytes set at 0x00, 0x00, 0x00 and 0x01. the payload bytes are set to 0x6a. tx link fifo length definition (0x008b-0x0092) registers are used to set the tx link utopia fifo size. the total number of cells in all the tx li nk utopia fifos, tx ima utopia fifo and tx link fifo (includes the links used in ima mode and the links used in tc mode) is limited to 118. idle cells are transmitted on the tc serial interface until the bit corresponding to the link in the utopia input link phy enable (0x0050) register is set. then, the at m user cells are transferred from the input utopia port to the tx serial port. 3.0 the atm receive path the receive path corresponds to the cell flow from the ph y (serial tdm) interfaces to the atm utopia interface. the mt90222/3/4 provides cell delineation and optional ce ll filtering to discard unassigned or idle cells on each link. the incoming cells are stored in the external ram, required in ima mode, to perform cell recovery due to delay variation between the links introduced by the network. 3.1 cell delineation function this block provides the circ uitry necessary to perform f unctions such as cell delineation (cd), cell payload de-scrambling, hec verification and filt ering of idle (non-ima) cells. the cd circuit delineates atm cells received from the payload of the t1, e1,j1 or dsl frame through the flexible tdm interface. when performing delineation, valid hec calculations are interpreted to indicate cell boundaries. the cd circuit performs a sequential hunt for a correct hec sequence. while performing this hunt, the cell delineation state machine is in the hunt state. figure 7 depicts a state diagram of the cell delineation operation. atm in cell_in_control cell ram tx link utopia fifo[n] p/s link [n] serial streams transmitter output controller and cell distribution
mt90222/3/4 data sheet 42 zarlink semiconductor inc. . figure 7 - cell delineation state diagram when a valid hec is found, the cd circuit locks on the cell boundar y and enters the presync state. the presync state keeps checking the hec to ensure that the previous indication was not fa lse. false indications are interpreted to mean the circuit is not tracking valid at m cells. after entering the presync state, the first false indication triggers a transition back to hunt state. if the presync state hec is correct, then a transition to the sync state occurs after ? ? cells (delta in itu i.432) are correctly received. in the sync stat e, the cd circuit treats the incomi ng atm cell stream as stable and the mt90222/3/4 functions normally. while in the sync state, if an incorrect hec is obtained ? ? consecutive times (alpha in itu i.432), cell delineation is considered lost and a transition is made back to the hunt state (see figure 5). as defined by the itu i.432 recommendations, the valu e of alpha and delta deter mine the robustness of the delineation method. the value of alpha and delta for the cell delineation state machine are defined in the cell delineation (0x00c9) register. only one set of values is defined for the sixteen cell delineation state machines. the status of the cd state machine for each link is available in bits 0 through 15 of the cell delineation status (0x00e6) register. the itu i.432 suggested values are: alpha = 7; and delta = 6. loss of cell delineation (lcd) is detected by counting t he number of incorrect cells while in hunt state. the mt90222/3/4 provides an internal loss of delineation (0x00c8) register to set the thre shold for this count. a value of 360 in the lcd register would correspond to 79 msec for e1 and 100 msec for t1 applications. the lcd state for each link is available in bit 1 of the irq link status (0x0435 - 0x4444) registers, and in bit 6 of the rx link id number (0x00e3) register. the lcd and end of lcd status bit reports the current cond ition of the cell delineation state machine at the time it is read, and can optionally generate an interrupt (irq). table 3 provides the time, in microseconds, for the cd circuit to receive a full atm cell fr om the t1 and e1 frame payloads. table 3 - cell acquisition time format average cell time ( s) t1 276 e1 221 hunt valid hec (byte by byte) presync sync alpha consecutive incorrect hec (cell by cell) delta consecutive correct hec (cell by cell) incorrect hec (cell by cell)
mt90222/3/4 data sheet 43 zarlink semiconductor inc. while the cell delineation state machine is in the sync stat e, the verification circuit im plements the state machine shown in figure 8. figure 8 - sync state block diagram in normal operation, the hec verification state machine rema ins in the ?correction? stat e. incoming cells containing no hec errors are passed to the receive ima block (rx ima) . incoming single-bit errors can be corrected if required by the application (i.e., single bit er ror correction can be enabled or disabled). after correction (when enabled), the resulting atm cell is passed to the icp processor block for ima sequencing control (ima mode) or rx link utopia fifo (tc mode). if a single or multi bit error occurs, the state machine transitions to the ?d etection? state. when a cell with a good hec is detected, the state machine returns to the ?correct ion? state. the hec calculation normally includes the atm forum polynomial (x 6 + x 4 + x 2 + 1). the use of the polynomial can be di sabled by writing to bit 1 or 9 of the rx link control (0x00c0-0x00c7) register. 3.1.1 cell delineation with sync signal when a serial tdm stream is used with a sync signal su ch as a tdm frame pulse, byte alignment is guaranteed. as a result, the hunt algorithm searches for the cell boundar y based on a predefined number of bytes. if it fails, the hunt algorithm shifts one byte and tries again. 3.1.2 cell delineation without sync signal when a serial tdm stream is used without a sync signal , byte alignment is not guaranteed. the hunt algorithm searches for the cell boundary based on a predefined number of byte s. if it fails, the hunt algorithm shifts one bit and tries again. when the hunt algorithm succeeds, it will have determined both the cell boundary and the byte alignment. 3.1.3 de-scrambling and atm cell filtering the cd circuit can de-scramble the cell payload field. the de-scrambling algorithm can be enabled or disabled using bit 5 or 13 of the rx link control (0x00c0-0x00c7) registers. the mt90222/3/4 can be programmed, using the rx link control (0x00c0-0x00c7) registers, to discard received atm cells with hec errors using bits 2 and 10. hec error correction is optional and can be enabled by the cpu. when the option to correct an incoming hec value with 1 bit error is selected, the hec is corrected and the ce ll is not counted as a cell with a bad hec. if the option to remove the cells that are received with a bad hec is selected , then the incoming cells are replaced by a filler cell (in ima mode) or discarded (in tc mode) . the counter is not incremented if the hec value is corrected, when the option is enabled. incoming idle and unassigned cells can be detected and dropped automatically. correction cell accepted detection cell discarded hcs single bit error detected (corrected or dropped) hcs multi-bit error dete cted (cell discarded) no hcs errors detected delta consecutive correct hcs?s (presync state) alpha consecutive incorrect hcs?s jump to hunt state atm cell delineation sync state
mt90222/3/4 data sheet 44 zarlink semiconductor inc. figure 9 - mt90224 receiver circuit in ima mode 3.2 atm receive path in ima mode the block diagram at figure 9 illustrates the mt90224 im a mode receive path. the receiver must rearrange the incoming bit streams from up to 16 li nks into a single utopia cell stream. 3.2.1 icp cell processor in ima mode, the transmitter inserts special icp cells in the various outgoing streams every m atm cells to comply with the ima specification. the receiv e block uses these icp cells to synchr onize with the far end transmit side and to reconstruct the original atm cell sequence. 3.2.2 ima fr ame synchronization the mt90222/3/4 implements ima frame sy nchronization state machines (ifsm) for each link, as described in section 11 of the ima specification. the values of alpha, beta and gamma are programmable through the ima frame delineation (0x00ca) register. their values are the same for all links. after the link is programmed to be in ima mode by writing to the rx link control (0x00c0-0x00c7) register, the ima frame state machine is enabled. at the same time, the parameter?s values of the rx link are latched in internal reference registers and are used to de termine whether the received icp cell meets the valid icp cell criteria to determine ima frame synchronization. proc. icp ima cell delin. s/p frame machine rxck rxsync dsti ram controller rx scheduler utopia interface rate recovery recovered cell clk ram area rx cell buffer state link info registers micro proc. icp ima cell delin. s/p frame machine rxck rxsync dsti state [0] [15] tdm ring control from tx block to tdm ring
mt90222/3/4 data sheet 45 zarlink semiconductor inc. incoming icp cells are automatically detected by the icp proc essing block. as soon as one valid icp cell is received, the ima frame state machine moves to the ima presync state. when gamma-valid icp cells are received, the state machine moves to the ima sync state. in the im a presync state, one errored or missing icp cell causes the state machine to return to the ima hunt state. in t he ima sync state, the state ma chine transitions to the ima hunt state by any of the following events: ? one missing icp cell ? alpha consecutive invalid icp cells ? beta consecutive errored icp cells after the received information is validated, the ima group is configured by writing to the rx reference link control (0x0209 - 0x0210) , the rx link control (0x00c0-0x00c7) and rx recombiner (0x0201 - 0x0208) registers. bits 3 and 2 of the rx state (0x00e4) register report the ima frame state ma chine state for a selected link. when in ima hunt mode, the information requir ed to perform the verification is extracted from the icp cells received. the ima frame state machine status (0x00e5) indicates whether a link?s ifsm is in a synchronized state. each link has one corresponding bit in this register. 3.2.3 link information all required link information for verification and link valida tion is extracted from the received icp cells. the ima id, link id (lid), reference link number, icp cell offset and frame length can be read and validated before enabling an ima group link. software obtains this information by writing to the rx load values (0x00dc) register to select a link and then reading the rx link ima id (0x00de) , rx icp cell offset (0x00df) and rx state (0x00e4) registers. this information can also be obtained by collecting all the received icp cells in the rx icp cell buffer and then processing the contents of th e icp cell (i.e., writing to the rx cell type ram (0x0100 and 0x0101) register and then reading from the rx icp cell buffer). the contents of the link information registers should be read and validated after enabling the rx tdm link in the rx link control (0x00c0-0x00c7) register and before enabling the ima mode. the link information can be accessed when a link is either in tc or ima m ode (but will not be upd ated in ima mode). 3.2.4 rx oam label the rx oam label is treated differently than the other link?s parameters. four user defined oam label (0x00cc-0x00cf) registers (1 register per 2 rx ima groups) are used to defined the rx oam label. its value is written by the software and can be changed at any point in time. however, the rx oam label has to match the value contained in the rx icp cell for the ima fram e state machine to reach the active state. 3.2.5 out of ima frame (oif) condition status bits in the rx oif status (0x00d9) register, one bit per link, report oif conditions. the status bit latches an oif condition which corresponds to a transition of the ifsm from sync to hunt. the oif condition is reported as a status bit only and cannot generate an interrupt. the status bit is cleared by writing a 0 to the corresponding bit. there are 16 oif counters, one per link. for each oif tr ansition, the 8-bit counter associated with the link is incremented by one. the counter can be read with i ndirect access when issuing a load command with the rx load values (0x00dc) register. the counter can be cleared by writing to the rx oif counter clear command (0x00da) register.
mt90222/3/4 data sheet 46 zarlink semiconductor inc. 3.2.6 loss of ima frame (lif) synchronization a link is declared out of ima frame (lif) synchronization state when the ifsm goes in hunt mode for ?gamma +2? frames after it was in sync state. loss of ima frame (lif ) and end of lif can optionally generate an interrupt (irq). this condition is latched in bits 2 and 10 of the irq link status (0x0435-0x0444) registers. refer to section 6.2.2 irq link status and irq link enable registers for more details. the lif status bit reports the current condition of the ima frame state machine at the time it is read. 3.2.7 filler cell handling the mt90222/3/4 sc ans each incoming cell received fo r the filler cell indication co de. filler cells are written to external ram to keep the ima frame aligned. they are automatically discarded after being read from the external ram by the recombiner. 3.2.8 stuff cell handling each incoming icp cell received is scanned for the stuff indi cation code. stuff cells are inserted at the transmit end as two identical and consecutive icp cells with the link st uff indication bits set as defined in the ima specification. the mt90222/3/4 automatically discards o ne of the two stuff cells without stori ng it in external ram. the other is kept and processed as a regular icp cell. ima frame synchronization is maintained for all cases (except case 7, o-19 optional requirem ents) as described in figure 20 of the ima specification. 3.2.9 received icp cell buffer an internal buffer is implemented to collect cells from t he rx tdm links for analysis by the software. this storage unit has a circular buffer for each link and contains up to three cells per link. the buffer can selectively collect: ? all valid cells received on a rx tdm port ? all valid icp cells ? all valid icp cells which contain new information (as indica ted by the scci field, valid only when the link is in ima mode) ? no cells the type of cells collected is defined in the rx cell type ram (0x0100 and 0x0101) registers. a status bit and a maskable irq alerts the software when a new cell is waiti ng for processing in a specific link. these are found in the irq link status (0x0435-0x0444) and enable (0x0445-0x0454) registers. software can directly access the cells in the rx buffer through a two-cell-w ide access window using rx ima icp cell (0x0800 - 0x0bff) . this access window can be advanced, one cell at a time, by issuing a command to move the internal pointer to the next cell. since the window accesses two cells, the last processed cell can be accessed at the window?s base address and the new cell at the base address plus 0x20. the rx cell level fifo status (0x0106) register is used to read the level of any of the 16 rx icp cell buffers. a ?0? in this register signifies that no new cell has been re ceived. a ?2? indicates the possi bility that one or more cells have been missed (overflow condition). the cell in the last entry of the circular buffer is a temporar y buffer (scratch pad). if, for example, the cell fifo level is 2, it is constantly overwritten by any new valid incoming cell. when the level is 0, the cell that is at the window?s base address is never overwritten as is kept for reference. the rx cell buffer increment read pointer (0x0105) register is used to advance the access window by 1 cell at a time. upon the command, the buffer level is decreased by 1. when the level reaches 0, the window is not advanced anymore.
mt90222/3/4 data sheet 47 zarlink semiconductor inc. during the start-up phase, the software can choose to co llect all valid icp cells from a rx tdm port and determine if the parameters are acceptable to proceed to start-up an ima group. in normal ima operating mode, the software will choose to co llect only valid icp cells with changes. the status and control change indication (scci) is monitored for all valid icp cells received. if the scci field indicates a change in the icp cells, they are put aside for processing by software. to accelerate the processing of icp cells that contain changes, any byte of the last and next processed icp cell can be accessed directly. to reduce the total processing time by the software, only those bytes that need to be read are accessed. the storage unit keeps the last read icp cell and has room for up to three new icp cells. 3.2.10 rate recovery the mt90222/3/4 computes the internal rx ima data cell rate (idcr) for each ima group. the cell rate of the reference link is integrated over a progr ammable period of time. software must specify the reference link for the ima group in the rx reference link control (0x0209 - 0x0210) registers and the period of integration in the rx idcr integration (0x0219 - 0x021c) registers. refer to tx ima data cell rate in section 2.4.5. the rx preprocessor is also available to aid the compar ison of cells. see section 6.4. as an option, the link to be used as a reference link can be extracted automatically from octet 14 of the received icp cell. this option is selected by bit 4 of the rx reference link control (0x0209 - 0x0210) registers. 3.2.11 cell buffer/ram controller the received cells are temporarily stored in external memory buffers until they can be correctly re-ordered for output. memory size depends on the number of links and the maximum delay allowed between the links. the memory requirements for different configurations are listed in table 4: the memory is organized in blocks of 64 bytes. each block can hold one cell. the following equation can be used to determine the maximum delay value or th e required ram size for a determined delay: to simplify the ram interface and pin loading, the mt90222/3/4 supports th e following six, register selectable, external memory configurations: ? one 32 kbyte sram device ? two 32 kbyte sram devices ? one 128 kbyte sram device ? two 128 kbyte sram devices ? one 512 kbytes sram device ? two 512 kbytes sram devices maxdelay = [ ramsize ] 64 1 (16) [ 1celltime ]
mt90222/3/4 data sheet 48 zarlink semiconductor inc. . 3.2.12 cell sequence recovery when an ima group is active, the ima recombiner manages the pointers to the external ram write and read location for the stored atm cells. a cell is read out from the buffer located in the external ram corresponding to the lowest link id (lid) of the ima group and placed in the rx ima ut opia fifo. after a complete cell read, a read pointer is set to the buffer corresponding to the next lid. at the following i dcr clock cycle, the next av ailable cell is read. icp cells are skipped and filler ce lls are discarded. this oper ation is done in a roundrob in fashion based on the lid value for each ima group link. faulty conditions (i.e., bu ffer overflow, excessive dela y) are reported through the irq link status (0x0435-0x0444) and irq ima overflow status (0x0420-0x0427) registers. 3.2.13 delay between links the delay values between links reflect the various transit delays though the network. in order to rebuild the original atm cell sequence, the link that exhibits less transport delay has to be stored unt il the data from the slowest link (the link having the largest transport delay) has arrived. the link that exhibits th e largest transport delay will be the link that requires the least cells to be stor ed. conversely, the line that exhibits t he least transport delay is the link that requires the largest number of cells to be stored. as a network parameter, the delay on a link should be constant. the delay between links should only change when links are replaced, added to a group (i ntroducing a new greatest or least del ay link) or removed from a group (removing a greatest or least delay link). indirect access is provided to internal registers which hold the various link delay values. the link number and delay type are first selected by writing to the rx delay select (0x02aa) register. after 2 system clock cycles, the 11-bit value in the rx delay (0x0285) and the rx delay link number (0x0286) registers are upda ted and can be read. the valid delay types are: the maximum delay over time , the current maximum delay and the current minimum delay for an ima group and the current delay values for any link. the delay values can be converted to time values by multip lying the number of cells by the conversion factor listed in the table 5. memory size (kbytes) delay (msec) t1 links e1 links 32 kb 8 6 64 kb 16 13 128 kb 34 27 256 kb 69 55 512 kb 140 112 1024 kb 281 225 note: assuming a guardband of 4 cells table 4 - differential delay for various memory configuration link type time per cell (msec) t1 isdn (23 ch. per frame) 0.288 t1 (24 ch. per frame) 0.276 e1 (30 ch. per frame) 0.221 table 5 - conversion factors time/cell (msec)
mt90222/3/4 data sheet 49 zarlink semiconductor inc. 3.2.13.1 rx recombiner delay value the icp cell from each link of the same ima group is us ed to determine the external sr am read and write pointers. the distance between the read and write pointers is referred to as the reco mbiner delay. setting the recombiner delay to the maximum acceptable delay results in a fixed reco mbiner delay that is not op timum. for example, setting recombiner delay to 25 msec when the worst case delay is 12 msec results in an additional, unnecessary delay of 13 msec. the minimum recombiner delay would be the current worst case differentia l delay. in the example above, the recombiner delay would be set to 12 msec. in this case, a link with larger transport delay than the current worst value cannot be added to an existing ima group: the cells from this slower link have not arrived when the cells sequence is rebuilt, as the read pointer was set us ing the previous worst case link. if this slower link is to be added, then the recombiner process has to stop for the time required to receive the cells on the slower link and then the recombiner process can resume. this causes disruptio n in the operation of the recombiner a nd will affect the cell delay variation (cdv). to provide an optimal recombiner delay, the mt90222/3/4 adds a guardband delay to the current worst case recombination delay when the ima group is first star ted up. guardband delay is pr ogrammable and minimizes the number of disruptions that would otherwise occur in accommodating link delays exceeding the current worst case. the guardband delay value is specified fo r each ima group by writing to the rx guardband/delta delay (0x0287-0x028e) registers. it should be the smallest value possible consistent with minimizing the disruptions (the smallest allowed value is 4). when operational, the val ue of the guardband delay corresponds to the delay value of the link having the greater transport delay (the link where the data is the last to arrive to the mt90222/3/4). 3.2.13.2 rx maximum operational delay value the various delays on links of the same ima group ar e measured and compared to the programmed ?maximum allowable value? stored in the rx maximum operational delay (0x029a-0x02a1) registers for the ima group. this value corresponds to the worst delay value that is expected. this value cannot be larger than the number of cells that can be stored in the external memory. the smalle st ?maximum allowable value? is four cells. these values are independently established for ea ch of the four ima groups. 3.2.13.3 link out of delay synchronization (lods) if a link to be added is slower and cannot be accomm odated by the present guardband, an lods signal is generated and the link delay value is re ported negative. the value reported is wi th respect to the read pointer and represents the minimum number of cells that has to be added to the present guardband before adding the link in the ima group. see paragraph 3.2.13.6 incrementing/decrementi ng the recombiner delay for more details. if a link to be added is faster and would cause its write pointer to be set beyond the rx maximum operational delay (0x029a-0x02a1) programmed value, then the link is reported to be faulty through an lods condition. the recombination process will not be affected as long as the amount of delay is not larger than the total number of cells in the external memory. lods will also be reported if, during oper ation, the delay of a link changes to ex hibit higher or lower delay resulting in a negative delay value or a value beyo nd the rx maximum operating delay value. lods events are reported by the irq link status (0x0435) register and investigated by selecting the current maximum delay using the rx delay select (0x02aa) , rx delay register (0x0285) and rx delay link number (0x0286) register . link out of delay sychronization (lods) and end of lods can optionally generate an interrupt (irq).
mt90222/3/4 data sheet 50 zarlink semiconductor inc. 3.2.13.4 negative delay values if the recombiner process is enabled for a link that exhi bits a negative delay value, t hen the recombiner process will be suspended until the write pointers are moved in such a wa y that the delay is reported with a positive value of 4. the recombiner process will then resume and no cells wi ll be lost. the same behavior applies if the delay value of a link which is part of the round robin process (recombi ner bit on) becomes negative: the recombiner process will be suspended until the delay value becomes positive wi th a value of 4. the latter condition can happen under severe error conditions if the recombiner process of the faulty link is not disabled. 3.2.13.5 measured delay between links the values and delay type for a selected link(s) or ima group can be read using the rx delay select (0x02aa) register. ima group delay types include: the maximum delay ov er time; the current maximum delay and the current minimum delay of an ima group. current link delay repo rts the current delay of a link. these values are all reported through a common rx delay (0x0285) register. the value is in number of cells. all delay values include the guardband delay value. the rx delay link number (0x0286) register reports the lin k number associated with the delay value that is currently in the rx delay (0x0285) register, with the exception for the maximum delay over time value, where the link number report ed is not valid (reports value of 0). the maximum delay over time value can be reset at any time by wr iting a clear command to bit 6 in the rx delay select (0x02aa) register. note t he value of the maximum delay over time is updated once per ima frame, hence it an take up to one ima frame for the value to be updated afte r it is reset. a value of 0xfe00 (negative 0) is read immediately after a reset command. the differential delays can be easily obtained by subtracting the delay values of the links. 3.2.13.6 incrementing/decr ementing the recombiner delay if a link to be added has a delay value which falls beyond the worst current delay valu e, then there are 2 options: either reject the link or re- adjust the pointers. to re-adjust the pointers , the number of cells to be added (delta) is specified and corresponds to the am ount of extra delay to be added to the current recombination delay. the additional delay is first programmed in the guardband/delta delay (0x0287-0x028e) registers and then a command to increase the delay is issued (using the increment delay control (0x0281) and decrement delay control (0x0282) registers). the mt90222/3/4 device stops the recombiner process for the amount of time specified and then resumes the recombiner process. no cells are lost but there is an effect on the cdv. the increment process is completed when the control bit in the increment delay control (0x0281) or decrement delay control (0x0282) register is returned to a 0 value. if the link exhibiting the longest trans mission delay is removed, the recomb iner delay can be reduced accordingly. when such a correction occurs, the number of cells corres ponding to the delay correction will be lost. to reduce the impact of this correction, its implementation can either be immediate or delayed. the increment delay control (0x0281) and decrement delay control (0x0282) registers are used for this purpose. the amount of delay to be removed (i.e., number of cells) in the recombiner process is controlled by the rx guardband/delta delay (0x0287-0x028e) register. alternatively, the links can all be placed in blocking mode for the transition period to avoid losing any cells. if a decrement delay command is issued which would result in a negative delay value on one or more links, the following action will take place: the read pointer is re -adjusted as required by the decrease delay command and since the delay is negative, the recombiner process is suspended un til the delay on all the links at least reach a positive value of 4. then, the recombiner process will resume.
mt90222/3/4 data sheet 51 zarlink semiconductor inc. 3.2.14 rx ima group start-up a quick initialization sequence for the rx ima group could be as follows (default values can be used for some registers). (note: the startup procedure below is to indicate the most important step s. a more detailed and complete sequence can be found in the zarlink ima core software).for mt90222 only groups 0,1,2 and 3 are used. ? configure the sram parameters using the sram control (0x0299), rx external sram control (0x0284) and global debug bit in the icp cell ram debug (0x0108) registers ? configure the cell delineation and ima frame state machines parameters by writing to the cell delineation (0x00c9), loss of delineation (0x00c8) and ima frame delineation (0x00ca) registers ? write to the rx link control (0x00c0-0x00c7) register to select the rx options ? configure the rx serial port(s) by writing to the tdm rx link control (0x0700-0x070f) register ? configure the rx ima utopia port by writing to the utopia output group phy enable (0x0011) and utopia output group address (0x0008-0x000b) registers ? validate the ima parameter values received over the tdm links and configure the link in ima mode using the rx recombiner (0x0201-0x0208) and the rx link control (0x00c0 - 0x00c7) register ? when ready, start the recombiner process by writing to the rx recombiner (0x0201-0x0208) register 3.2.15 link addition the mt90222/3/4 supports software controlled link addition to an existing rx link group. such an addition can be used to increase available bandwidth. the added link receives filler cells until the far end (fe) tx side is active. during this time, the new link?s delay is measured and compar ed with the current operatin g limits. the link is either rejected or accepted. the operational delay can be corrected if required as described in 3.3.13.6 incrementing/decrementing the recombiner delay. af ter synchronization is achieved, the added link can be included in the recombiner algorit hm using bit 4 or 12 of the rx recombiner (0x0201-0x0208) register. the link will be effectively included in the ima group when the corr esponding bit in the enable recombiner status (0x02ad) register is set. a link may also be added to an ima group when the first us er cell is received. this is done by writing to the rx recombiner delay control (0x0283) register. 3.2.16 link deletion there are two reasons to deactivate a link: ? the bandwidth required decreases or ? an existing link becomes faulty. both link deactivation procedures spec ified in the ima specification are s upported under the control of software. the command to disable the recombination process for a link is issued by writing to bit 4 or 12 of the rx recombiner (0x0201-0x0208) register. if the delay of the link to be removed is not the wors t delay, then no pointer correction is required and the recombiner bit (i.e., bit 4 or 12 of rx recombiner (0x0201-0x0208) register) for the removed link should be set to 0. if it is the worst case delay, then the pointer values c ould be corrected to reduce th e amount of additional delay introduced by the recombiner. to do this, the pointers need to be changed (advanced). this results in reducing the number of cells (the amount of time) required for the recombiner process.
mt90222/3/4 data sheet 52 zarlink semiconductor inc. to reduce the impact of this correction, its implementat ion can either be immediate or delayed. a command in the increment delay control (0x0281) or decrement delay control (0x0282) register is used for this purpose (refer to 3.3.13.6 incrementing/decrementing the recombiner delay, for more details). 3.2.17 disabling an ima group before an ima group can be disabled, the software should ens ure that no user cells are left in memory. as part of the higher level handshaking, the tx fe should have sent f iller cells for a while for the rx side to process all the user cells that could be in the external memory. the procedure to follow is to stop the recombination pr ocess and then wait for the enable process to be reported inactive (in the enable recombiner status (0x02ad) register) before re-assigning the link to another ima group or to tc mode. 3.3 the atm receive path in tc mode up to sixteen incoming serial (typically tdm) lines can be connected to the mt90222/3/4 receiver and forwarded to the utopia l2 interface served by an external atm-layer device. figure 10 ill ustrates four of the sixteen possible utopia ports that can be addressed through the utopia interface. the size of the rx utopia fifo is fixed at 4 cells. t he idle cells are automatically removed at the rx tdm block and all other valid received cells are tr ansferred to the rx utopia fifo. th e fifo is cleared when the rx utopia port associated with the fifo is enabled. figure 10 - example of tc mode operation (using four of sixteen possible utopia-output ports) 4.0 description of the tdm interface the transmit tdm blocks are independent of the receive tdm blocks. the tx port of a framer can be connected to any of the mt90222/3/4 tx utopia input ports and the rx port of a framer can be connected to any of the mt90222/3/4 rx utopia output ports. the tdm interface provides a variety of modes to work wi th different t1/e1/dsl framer s for various applications. in general, there are four major modes: single mode, wi re-or mode, multiplex mode and non-framed mode. each mode can be further divided into several minor modes. rxck rxsync dsti s/p rxck rxsync dsti rxck rxsync dsti rxck rxsync dsti utopia cell interface system clock s/p s/p s/p delineation idle cell removal cell delineation idle cell removal cell delineation idle cell removal cell delineation idle cell removal
mt90222/3/4 data sheet 53 zarlink semiconductor inc. 4.1 single mode in this mode, all links are active and can be used. it s minor modes of operation include generic 1.544 mhz mode (f-bit and 24 time slots), generic 2.048 mhz mode (32 time slots), and st-bus mode (32 time slots). mapping registers are used to determine when a time slot is used to carry the atm traffic. there are two 16-bit mapping registers for each tdm tx and for each tdm rx links. each bit of the 2 registers (total of 32 bits) controls one time slot. a bit value of 1 corresponds to an active ti me slot. a value of 0 corresponds to an inactive time slot and the output is in high impedance mode for that time sl ot. the tdm tx link is independent of the tdm rx link and can have different mapping (using di fferent time slots and op tionally a different num ber of time slots). fractional t1/e1 and nx64 channel modes are implemented by programming bits in the m apping registers to enable the use of the required time slots. 4.1.1 single mode - generic 1.544 mhz this is also known as t1 generic mode. in this mode, da ta rate is 1.544 mb/s, clock is 1.544 mhz and frame pulse is 8 khz. a frame is 193 bits long and a frame pulse is pr esent (either generated or accept ed as input). the first bit, indicated by the frame pulse, is not used to carry any usef ul information; it is in high impedance on tx link and is ignored on rx link. the 24 time slots (192 bits) are controlled by the lowest 24 bits of th e mapping register associated with a link. fractional t1 is supported by activating (selecting) any of the fi rst 24 time slots defined in the mapping register. figure 11 - single m ode - generic 1.544 mhz this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. data rate (bits 6:5) = 00 multiplex mode (bits 4:3) = 00 clock and sync format (bit 2) = 0 cell delineation mode (bit 10 of tdm rx link control only) = 0 4.1.2 single mode - generic 2.048 mhz this is used for generic nx64 connections, where n can be any number from 1 to 32. in this mode, data rate is 2.048 mb/s. a clock of 2.048 mhz is used and the frame pulse is indicating the first bit of th e first time slot of a frame of 32 time slots. the mapping register s are used to determine the number of ti me slots used and their position in the frame. this enables a direct interface to existing t1 or e1 framers and opens up the option to interface to generic nx64 devices. fractional t1/e1 is supported as well by sele cting the time slots that ar e used to carry atm traffic. t1 frame bit cells at dstx0-15 bit 193 bit 1 bit 2 ... serial bit stream bit cell ... bit cell txsync rxsync txck rxck ... ... ... unused or high impedance note: both frame pulse polarity and clock edge are programmable.
mt90222/3/4 data sheet 54 zarlink semiconductor inc. figure 12 - single mode - generic 2.048 mhz this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. data rate (bits 6:5) = 01 multiplex mode (bits 4:3) = 00 clock and sync format (bit 2) = 0 cell delineation mode (bit 10 of tdm rx link control only) = 0 4.1.3 single mode -st-bus this is used for t1/e1 connection with st-bus, where data rate is 2.048 mb/s, clock is 4.096 mhz and frame pulse is 8 khz. a standard st-bus mode is supported with 32 time slots in each frame. the frame format and clock speed meet the st-bus or mvip standard. the mapping register s are used to determine which of the 32 time slots are used to carry tdm traffic. figure 13 - single mode - st-bus st-bus bit cells (dstx0-15) channel 31 bit 0 channel 0 bit 7 serial bit stream bit cell txsync rxsync channel 0 bit 0 channel 1 bit 7 bit cell ... ... ... ... ... ... ... ... ... txck rxck ... ... bit cell bit cell note: both frame pulse polarity and clock edge are programmable. serial bit stream bit cell bit cell ... ... st-bus bit cells (dstx0-15) channel 31 bit 0 channel 0 bit 7 txsync rxsync txck rxck channel 0 bit 0 channel 1 bit 7 ... ... ... ... ... ... bit cell bit cell note: frame pulse polarity and clock edge are fixed in st-bus mode.
mt90222/3/4 data sheet 55 zarlink semiconductor inc. this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. data rate (bits 6:5) = 01 multiplex mode (bits 4:3) = 00 clock and sync format (bit 2) = 1 cell delineation mode (bit 10 of tdm rx link control only) = 0 4.2 wire-or mode in this mode, two or four links are logi cally or?ed together to share a single st ream. this is partic ularly useful for fractional t1/e1 applications where links using different time sl ots can be multiplexed t ogether onto a single stream in order to facilitate the interfac e to a single t1 or e1 framer. links that are or?ed together can have any one of th e single mode discussed in section 4.1. to avoid any contention, mapping registers of those links must not have the same bit set. all links in wire-or mode must be configured in t he same as they were in single mode, except for tdm link control registers. two minor modes are availabl e, 2-link grouping and 4-link grouping. 4.2.1 wire-or mode - 2 link grouping two links in a pair are or?ed together by using this mo de. the links that are paire d are pre-determined: link 0 is paired with link 1, link 2 is paired with link 3 and so on . when link 0 and link 1 are paired, the pins associated with link 1 cannot be used and are tri- stated, however, bit 7 of its tdm tx(rx) link control registers must be set. the two links operate using the clock and sync signals of link 0. the same logic applies for the other pairs. this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. note that both links in a pair must have the same settings. data rate (bits 6:5) = 00 or 01 multiplex mode (bits 4:3) = 01 clock and sync format (bit 2) = 0 or 1 enable (bit 7) = 1 cell delineation mode (bit 10 of tdm rx link control only) = 0 4.2.2 wire-or mode - 4 link grouping four links in a group are or?ed together by using this mo de. the links that are grouped are pre-determined: links 0, 1, 2 and 3 are grouped and the or?ed input/ output is available on link 0 only. pins associated with links 1, 2 and 3 cannot be used and are tri-stated, however, bit 7 of tdm tx(rx) link control registers for those three links must be set. the four links operate using the clock and sync signal of link 0. the same logic applies for the other groups. this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. note that all four li nks in a group must have the same settings. data rate (bits 6:5) = 00 or 01 multiplex mode (bits 4:3) = 10 clock and sync format (bit 2) = 0 or 1 enable (bit 7) = 1 cell delineation mode (bit 10 of tdm rx link control only) = 0
mt90222/3/4 data sheet 56 zarlink semiconductor inc. 4.3 multiplex mode a multiplex mode is offered by many multi-channel t1/e1 framers to multiplex several t1/e1 links on to one high speed data link. the same mode is available on mt90222/3/ 4, where two or four 2.048 mb/s links are multiplexed using a common clock of 8.192 or 16.384 mhz. in this majo r mode, two or four links running at 2.048 mbps are interleaved on a time slot basis (byte by byte) to provide a mu ltiplexed link at a data rate of 4.096 mb/s or 8.192 mb/s. in multiplex mode, links are treated or processed the same way as they are in single mode. the only difference is the way that data is carried on tdm bus. in single mode, each link uses its own tdm port to carry data, whereas in multiplex mode two or four links shares a single high speed port. as in wire-or mode, links in multiplex mode must be configured in the same as they were in single mode, except for tdm link control registers. when multiplexed mode is used, the time slots on the multiplexed links have to use a common synchronized clock source and frame pulse for the multiplexed links. multiplexi ng of fractional t1/e1 is also possible through the control of merged mapping registers. only st-bus mode, with tdm txck and txsync c onfigured as inputs, is supported in this mode. there are two minor modes in multiplex mode, 2-link multiplexing and 4-link multiplexing. 4.3.1 multiplex mode - 2 link multiplexing in this mode, two links of 2.048 mb/s are multiplexed onto a single link of 4.096 mb/s. the links that are paired are pre-determined: link 0 is multiplexed with link 1, link 2 is multiplexed with li nk 3 and so on. when link 0 and link 1 are multiplexed, the pins associated with link 1 canno t be used and are tri-stat ed, however, bit 7 of its tdm tx(rx) link control registers must be set. the two li nks operate using the clock and sync signals of link 0. the same logic applies for the other groups. as an example of this grouped multiplexing, the MT90223/224 supports eight high speed links on links 0, 2, 4, 6, 8 10, 12 and 14 and the mt90222 supports four high speed links on links 0, 4, 8 and 12. unlike single mode, the only clock format supported is st-bus mode when txck and txsync are inputs. the data rate is 4.096 mb/s. a clock of 8.192 mhz is used and the fram e pulse indicates the first bit of the first time slot of a frame of 64 time slots. the mapping regi sters of the 2 physical links are merged by bit-to-bit interleaving to form a larger mapping regist er supporting up to 64 time slots. this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x700-0x070f) by the following settings. note that both links in a pair must have the same settings. data rate (bits 6:5) = 10 multiplex mode (bits 4:3) = 01 clock and sync format (bit 2) = 1 enable (bit 7) = 1 cell delineation mode (bit 10 of tdm rx link control only) = 0 tx clock direction (bit 9 of tdm tx link control only) = 1 4.3.2 multiplex mode - 4 link multiplexing in this mode, four links of 2.048 mb/s are multiplexed onto a single link of 8.192 mb/s . the links that are combined are pre-determined: links 0, 1, 2 and 3 are grouped and the multiplexed input/output is available on link 0. when link 0 is used, the pins associated with links 1, 2 and 3 cannot be used and are tri-stated, however, bit 7 of tdm tx(rx) link control registers for those three links must be set. the four links operat e using the clock and sync signal of link 0. the same logic applies for the other groups. as an example of this grouped multiple xing, the mt90222/3/4 supports four high speed links on links 0, 4, 8 and 12.
mt90222/3/4 data sheet 57 zarlink semiconductor inc. unlike single mode, the only clock format supported is st-bus mode when txck and txsync are inputs. the data rate is 8.192 mb/s. a clock of 16.384 mhz is used and the fr ame pulse indicates the first bit of the first time slot of a frame of 128 time slots. the mapping registers of the 4 physical links are me rged by bit-to-bit interleaving to form a larger mapping register suppor ting up to 128 time slots. this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. note that all four li nks in a group must have the same settings. data rate (bits 6:5) = 11 multiplex mode (bits 4:3) = 10 clock and sync format (bit 2) = 1 enable (bit 7) = 1 cell delineation mode (bit 10 of tdm rx link control only) = 0 tx clock direction (bit 9 of tdm tx link control only) = 1 4.4 non-framed mode single mode, wire-or mode and multiplexed mode are all deal ing with framed data, that is, a frame pulse must be present to give both byte and fram e alignment. however, mt90222/3/4 also support a non-framed mode where only a serial bit stream and clock are avai lable for each link. moreover, a wide range of data rate is supported by this mode, which makes it particularly useful in ds l applications where the line rate may vary. when used in non-framed mode, rxsync must be de-assert ed. for example, if rxsync is defined as active low frame pulse (bit 0 cleared in tdm rx link control register), rxsync input pin must be tied to high. the same applies to txsync when it is an input pin. mapping registers must all be set to 0xffff in non-framed m ode. serial clock rate and data rate must be the same. moreover, bit mode cell delineation (bit 10 in tdm rx link control registers) must be se lected, and register 0x0741 must be written by 0x36. three minor modes are available in non-framed mode, resulting to different data rate and link number. 4.4.1 non-framed mode - 2.5 mbps in non-framed mode, all links are able to run from 0 up to 2.5 mb/s. on the transmit side, if the txck and tcsync are programmed as inputs, t xsync must be disabled state, and the transmitter will be "free running" and will output serial data continuously. if the txsync is defined as outp ut, a frame pulse is generated for every 256 txck cycles, but can be ignored. this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by the following settings. data rate (bits 6:5) = 01 multiplex mode (bits 4:3) = 00 clock and sync format (bit 2) = 0 cell delineation mode (bit 10 of tdm rx link control only) = 1
mt90222/3/4 data sheet 58 zarlink semiconductor inc. 4.4.2 non-framed mode - 5.0 mbps if a serial link of more than 2.5 mbps but less than 5.0 mbps data rate is required, this mode can be applied. for every two links in a pair, one is disabled and the other is able to run from 0 up to 5.0 mb/ s. the links that are paired are pre-determined: link 0 with link 1, link 2 with link 3 and so on. the link that will remain enabled in each pair is also pre-determined. they ar e link 0, 2, 4, 6, 8, 10, 12 and 14. for the pair of link 0 and link 1, the pi ns associated with link 1 cannot be used and are tri-stated. on the transmit side of link 0, if the txck and tcsync ar e programmed as inputs, txsync must be de-asserted, and the transmitter will be "free running" and will output se rial data continuous ly. if the txsync is defined as output, a frame pulse is generated for every 512 txck cycles, but can be ig nored. the same logic appli es for the other pairs. for any disabled link, its asso ciated registers are all disabled, except for mapping regi sters that must be set to all one. no other configuration is necessary for disabled links. when the link is part of an ima group , then both links that are paired have to be assigned to the same ima group number. this is done by writing to the rx recombiner register (0x0201-0x0208). this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by writing the following settings into those enabled links only. data rate (bits 6:5) = 10 multiplex mode (bits 4:3) = 00 clock and sync format (bit 2) = 0 cell delineation mode (bit 10 of tdm rx link control only) = 1 4.4.3 non-framed mode - 10.0 mbps if a serial link of more than 5 mbps but less than 10.0 mbps dat a rate is required, this mode can be applied. for every four links in a group, three ar e disabled and the other is ab le to run from 0 up to 10.0 mbps. the four links that can be grouped are pre-determined: link 0, 1, 2, 3 are one group; link 4, 5, 6, 7 are one group and so on. the link that will remain enabled in each group is also pre-determi ned. they are link 0, 4, 8 and 12. for the group of link 0, 1, 2 and 3, the pins associated with link 1, 2 and 3 ca nnot be used and are tri-stated. on the transmit side of link 0, if the txck and tcsync are programmed as inputs, txsync must be de-asserted, and the transmitter will be "free running" and will output serial data c ontinuously. if the t xsync is defined as output, a frame pulse is generated for every 1024 txck cycles, but can be ignored. the same logic applies for the other groups. for any disabled link, its asso ciated registers are all disabled, except for mapping regi sters that must be set to all one. no other configuration is necessary for disabled links. when the link is part of an ima group, then the four links that are grouped have to be assigned to the same ima group number. this is done by writing to the rx recombiner regist er (0x0201-0x0208). this mode is selected in tdm tx link control (0x0600-0x060f) and tdm rx link control (0x0700-0x070f) by writing the following settings into those enabled links only. data rate (bits 6:5) = 11 multiplex mode (bits 4:3) = 00 clock and sync format (bit 2) = 0 cell delineation mode (bit 10 of tdm rx link control only) = 1
mt90222/3/4 data sheet 59 zarlink semiconductor inc. 4.5 clock formats in any framed modes, the frame signal fo rmat can be one of two options. it ca n be of a generic format (active high or low during the first bit of the frame) or st-bus format (active low at the boundary of the frame). in the generic modes, the clock polarity can be selected to have a rising or falling edge at the bit boundary. the txck and txsync signals can be either outputs or inputs. 4.6 tdm loopback mode two loopback modes are provided where the tdm rx i nputs are internally routed back to the tdm tx outputs (remote loopback) with the rx block fully operational, and where the tdm tx outputs are routed back to the tdm rx inputs for test purposes (metallic loopback). the tx and rx links have to be programmed in the same mode for the loopback to operate properly. bit 8 of the tdm tx link control register (0x0600-0x060f) controls the remote loopback and bit 8 of the tdm rx link control (0x0700-0x070f) register controls the metallic loopback. to use remote loopback, txck and txsync must be conf igured as output sourcing from the rxck and rxsync of the same port. the loopback is on a per link basis with the limitation that physical links are paired: i.e., tx link 0 is connected to rx link 0 and so on. besides tdm loopacks, there is also a utopia loopback described in section 5.7. 4.7 serial to parallel (s/p) a nd parallel to serial (p/s) converters each serial tdm link has assigned s/p and p/s units. the p/s unit takes a byte from the cell ram and converts it to a serial bit stream. the s/p unit takes a byte from the ds ti input and converts it to parallel format for use by the cell delineation block. p/s and s/p units can be set-up differently on a per port a nd per direction basis (i.e., the transmit and receive function of the same port can use diff erent configurations). the fo llowing features are supported: ? programming links as t1 or e1 ? using st-bus and generic tdm modes ? enabling/disabling the p/s and s/p units (if they are disabled the associated outputs are tri-stated) ? selecting tdm timeslots as per mapping registers ? independently programming the polarity of rxck, txck, rxsync and txsync signals (generic tdm mode only) ? generating/accepting txsync and txclk signals to s upport most t1 and e1 framers (depending on the programmed mode) ? monitoring rxsync signal period and reporting t he unexpected occurrence of a synchronization signal ? monitoring txsync signal period (when defined as input) and reporting the unexpected occurrence of a synchronization signal ? generating a txsync pulse on every tdm frame when defined as output when the txck and txsync signals are outputs, the source for the txclk is software selectable from any of the rxck inputs or any of the four external refcks. the txsync signal is generated from the txck and is independent from (not al igned with) the rxsync or other txsync signals.
mt90222/3/4 data sheet 60 zarlink semiconductor inc. 4.8 clocking options txck and txsync can be either input or output signals. when txck and t xsync are inputs, they are generated by external circuitry. when txck and txsync are outputs, txck source is software selectable and can be any of the rxck signals or four external refck inputs (see figure 14). the txsync is generated from the txck signal. the rxck pins are always defined as inputs and th e proper signal must be provided to each input. figure 14 - txck and txsync output pin source options 4.8.1 verification of the rxsync period the rxsync signal is used to align the incoming dsti data to retrieve all the t1 or e1 channels. the rxsync pulse can be present for each tdm frame (8 khz) or once per superframe (an integer nu mber of frames, typically 12 or 16). the period and position of the rxsync is verified for each rece ive block independently. a status bit (1 per link) in the rxsync status (0x0730) register is set if th e synchronization pulse occurs at an unexpected time in the frame. the rx block will be re-aligned with this new synchronization pulse. 4.8.2 verification of the txsync period the txsync signal is used to align the outgoing dsto data to retrieve all the t1 or e1 channels. when defined as input, the txsync pulse can be present for each tdm fram e (8khz) or once per superframe (every 12 or 24 tdm frames). the period and position of the txsync is verified for each transmit block independently. a status bit (1 per link) in the txsync status (0x0633) register is set if the synchronization pulse occurs at an unexpected time in the frame. the tx block will be re-aligned with this new synchronization pulse. 4.8.3 primary and secondary reference signals two output pins are provided to simpli fy the external circuitry required when using an external pll. these two pins, pllref0 and pllref1, re-route any of the rxck signal s and drive the primary and se condary reference signals of a pll under software control. refer to se ction 8, application notes, for examples. rxck 0-15 pllref0 pllref1 cell delineation s/p p/s tx cell fifo dsto txck txsync dsti rxck rxsync rxck 0-15 refck 0-3
mt90222/3/4 data sheet 61 zarlink semiconductor inc. 4.8.4 verification of clock activity the mt90222/3/4 implements circui try to determine whether or not a selected clock signal is active. this feature is used to ensure a clock is operational bef ore using it as a source for one or more transmit links. a read of the txck status (0x0630), rxck status (0x0631) or refck status (0x0632) register indicates a faul ty clock if a bit is ?1?. a value of ?0? for these bits means that activity was obse rved on this clock. this circuitry does not measure the frequency of a clock signal, it only detects activity on the txck, rxck and refck signals. 4.8.5 clock selection the clock selection circuitry selects the desired clock signal and ensures a smooth, glitch free, transition between the current clock source and the new clock source. clock source activity can be verified using the txck status (0x0630), rxck status (0x0631) or refck status (0x0632) registers. 5.0 utopia interface operation the mt90222/3/4 supports the utopia l1 and l2 mode, 8 or 16 bit wide bus, with odd/even parity, for cell level handshake only.in 8-bit utopia mode maximum supported clock is up to 52 mhz and in 16-bit mode it is 33 mhz. each port can be assigned an address ranging from 0 to 30 . the address value of 31 is reserved and should not be used. the tx and rx paths of each ima group and each link in tc has its own phy address. these phy addresses are defined in the utopia input link address ( 0x0040-0x0047) registers, utopia input group address (0x0048-0x004b) registers, utopia output link address (0x000-0x0007) registers, and the utopia output group address (0x0008-0x000b) registers. the utopia input link phy enable (0x0050) and the utopia output link phy enable (0x0010) registers are used to enable the phy address of the links in tc mode. the utopia input group phy enable (0x0051) register and the utopia output group phy enable (0x0011) registers are used to enable t he phy address of the ima groups. the mt90222/3/4 utopia port uses handshaking signals to process data streams. the start of a cell (soc) is marked by the utopia soc sync signal. this signal is active during the transfer of the firs t byte/first word of a cell. the 52 bytes/26 words that follow the ar rival of the first byte/fir st word of a cell are interpreted as belonging to the same cell and are stored accordingly. the cell available status line (clav) is used to comm unicate to the atm controller whether the mt90222/3/4 has space for a cell in the phy address that was polled in the previous cycle. whenever there is space for a cell in the tx direction or a cell ready in the rx direction, the txclav and/o r rxclav signal will be dr iven high. if there is no space in tx direction and/or no cell is re ady in rx direction, the txclav and/or rxclav will be kept low. when the address does not correspond to any enabled phy address in side the mt90222/3/4, the txclav and rxclav signal are set to high impedance mode. the use of an external pull-down may be required for the proper operation of the utopia bus in mphy mode. note that the transmit or receive utopia clock frequencies do not have to be synchronized with the system clock but their frequencies cannot exceed the system clock frequency. important note: the mt90224/3/2 doesn?t support the back-to- back mode on rx side (atm output port). depending on which atm controller the mt 90222/3/4 interfaces to, there might be interoperability issues that affect the receive side communication. for details, please refer to technical note zlan-88: utopia interface between mt90224/3/2 and specific atm controllers. 5.1 atm input port the utopia interface input clock txclk is independent of the system clock. the utopia txclk can be up to 52 mhz for 8-bit mode and up to 33 mhz for 16-bit mode. the incomi ng cell is stored directly in the internal tx cell ram where the tx utopia fifos are implemented.
mt90222/3/4 data sheet 62 zarlink semiconductor inc. the utopia transmit clock (txclk) is checked against t he system clock. if the incoming byte clock frequency is lower than 1/128 of the system clock, bit 2 of the general status (0x040e) register will be set. this bit is cleared by overwriting it with 0. this aids in debugging as the presence of a utopia clock is required not only for data transfer but also for proper oper ation of the utopia registers. the total space for the utopia input cells for all ima groups and links in tc mode is 118. these 118 cells are shared between 24 tx utopia fifos and 16 tx link fifo s. the size (length) of each tx utopia fifo is defined by writing to the tx ima group fifo length definition (0x0093 - 0x0096) registers. the maximum value is 6 and the minimum value is 0 (in the case the phy port is not to be used). the size of the tx link fifo is defined on a per group using the tx ima control (0x0321-0x0324) registers. the device will not accept a cell from the utopia interface if the internal cell ram is full. status bit 0 in the general status (0x040e) register is set to 1 to indicate the ?no free cell in tx cell ram? condition. the status bit can be cleared by overwriting it with 0. note that the internal fifo level on the tx direction is updated after the complete cell is received. if the corresponding utopia port address is poll ed, that the cell available status signal could reflect space available whereas the fifo should be reported full. if a cell transfe r is initiated under these c onditions, the cells will be accepted and the next time the utopia port is polled, the cell availa ble status signal will report the correct state of the fifos. the utopia input block has the option to verify the hec of the cell coming from the atm layer. four different options are available and are sele cted by bits 1 and 0 of the utopia input control (0x0052) register. ? the ?00? option is used to always accept a cell from the atm layer. the hec is verified and if wrong, the utopia input counter associated with the utopia port for cells with bad hec is incremented. the mt90222/3/4 will re-generate a valid hec based on th e content of the 4-byte header that was received. ? the ?01? option is used to verify the hec of an incoming cell. if the hec value is wrong and if it can be corrected (1 bit error), then the cell is corrected and accepted as a good cell. the bad hec counter is not incremented if the hec is corrected. the bad hec counter is incremented if the hec value cannot be corrected. in this mode, the cell is always accept ed. the mt90222/3/4 will re-generate a valid hec based on the content of the 4-byte header that was received. ? the ?10? option is used to verify the hec on the incomi ng cell and discard the cell if the hec value is wrong. the bad hec counter is incremented if a cell is discarded. ? the ?11? option is similar to mode ?01? except that if the hec value cannot be corrected, then the cell is discarded. if the hec value is corrected, the bad hec counter is not incremented. 5.2 atm output port the mt90222/3/4 supports a 53 byte/27 words cell stream vi a the atm output port. cells at the atm output port are stored in the rx utopia fifo before being processed by the utopia interface. the output of the utopia interface can be stopped by the atm layer dev ice by de-asserting the rxenb* signal. the start of a cell is marked with the soc signal, which is active during the transmission of the first byte/first word of a cell. the following 52 bytes/26 words are belonging to the same cell. the rx byte clock (rxclk) can be up to 52 mhz and is check ed against the system clock. if the incoming byte clock frequency is lower than 1/128 of the system clock, bit 3 of the general status (0x040e) register will be set. this bit is cleared by overwriting it with 0. th is aids in debugging, as the presence of a utopia clock is required not only for data transfer but also for proper operation of the utopia registers.
mt90222/3/4 data sheet 63 zarlink semiconductor inc. overflow conditions in the rx utopia fifo associated with any of the 24 phy rx addresses cause a status bit to be set in either the irq link tc overflow status (0x0410-0x041f) or irq ima overflow status registers (0x0420-0x0427) register. these status bits are cl eared by overwriting them with 0. additionally, for each status bit there is an interrupt enabl e bit in the associated irq link tc overflow enable (0x0434) or rx utopia ima group fifo overflow irq enable (0x040c) register. when enabled, the status bit is reported in an interrupt register. see section 6.2 inte rrupt block for more details. the size of the rx utopia fifo is fixed at f our cells for the tc phy and ima group phy addresses. note that in the receive direction, the pa rity bit that is generated is not valid if the receive utopia clock is faster than 50 mhz. 5.3 utopia operation with a single phy a single atm layer device with a utopia l2 mphy port can be connected to the atm input port of one mt90222/3/4. another atm-layer device using the utopia l2 mphy input interface is used to receive atm cells from the mt90222/3/4. the address pins should be set to the va lue programmed by the management interface. 5.4 utopia operation with multiple phy when more than one mt90222/3/4 is connected to a single atm layer device the single txclav and rxclav scheme is used. direct status in dication and multiplexed stat us polling schemes are not su pported. the necessary polling is performed by the atm-layer device. the utopia interface transmit and receive addresses, provi ded by the atm-layer device, are used to de-multiplex the atm-cell stream to as many as eight mt90222/3/4s (as limited by the utopia l2 specification?s maximum of eight device loads and 31 addresses). the maximum total av ailable bandwidth for the serial lines served by each mt90222/3/4 device is 40 mbits/s (totalling 5 mby tes/s per mt90222/3/4 device). 5.5 utopia operation in tc mode in tc mode, each utopia port inside an mt90222/3/4 corr esponds to a physical serial tdm (t1, e1, j1, dsl) line. up to sixteen phy ports can be supported by one mt90 224. up to eight mt90222/3/4s can be connected to a utopia bus. the ports in the same device represent only one electrical l oad on the utopia bus. the mt90222/3/4 supports the up to 31 phy addresses as per utopia specification. please also refer to technical note zlan-88: utop ia interface between mt90224/3/2 and specific atm controllers, as there might be some limitations on maxi mum number of phy addresses supported depending on the type of atm controller that is interfaced with mt90224/3/2. the mphy address at the input port of mt90222/3/4 (txaddr[4:0]) is used to st ore the cell in one specific tx utopia fifo. the mphy address at the output port (rxaddr[4:0]) is used to retrieve the cells from the proper rx utopia fifo.
mt90222/3/4 data sheet 64 zarlink semiconductor inc. 5.6 utopia operation in ima mode in ima mode, many mt90222/3/4s, with up to eight ut opia ports each (one port per ima group), can be served by an external utopia l2 atm-layer device provided the ut opia limitation of 31 ports in total is observed. this provides up to 31 different logical ima-channels. note that port 31 (1f in hexadecimal format) is reserved. pease also refer to technical note zlan-88: utopia interface between mt90224/3/2 and specific atm controllers, as there might be some limitations on maxi mum number of phy addresses supported depending on the type of atm controller that is interfaced with mt90224/3/2. 5.7 utopia loopback with utopia loopback enabled , the tx utopia port will accept cells and loop these back to the rx utopia interface. the rx utopia interface will then output thes e cells.the utopia loopback is enabled by setting the bit 9 in utopia input control register (0x0052). with utopia loopback, only one phy address can be tested at a time . 5.8 examples of utopia operations modes figure 15 shows the connection of one atm device to one mt90224. figure 15 - atm interface to mt90224 figure 16 shows the connection of one atm device with more than one mt90224. txclk txaddr txdata rxenb* rxclav rxsoc txclav txsoc rxdata rxclk rxaddr atm txenb* mt90224 atm layer physical layer framer framer . . . . .
mt90222/3/4 data sheet 65 zarlink semiconductor inc. figure 16 - atm interface to multiple mt90224s figure 17 - atm mixed-mode interface to one mt90224 figure 17 illustrates the implementation of a mixed m ode using only 1 mt90224. links that are not used for ima groups are available in tc mode. unused links are programmed to set their outputs to high impedance mode. atm txclk txenb* txaddr txclav txsoc txdata rxclk rxenb* rxaddr rxclav rxsoc rxdata mt90224 framer framer atm layer physical layer txclk txenb* txaddr txclav txsoc txdata rxclk rxenb* rxaddr rxclav rxsoc rxdata mt90224 framer framer . . . . (ima group #1) (ima group #2) (3 links in tc mode) atm 3 utopia ports (tc) 16 layer device framer 1 utopia port 1 utopia port (8 links) (5 links)
mt90222/3/4 data sheet 66 zarlink semiconductor inc. 6.0 support blocks 6.1 counter block the mt90222/3/4 includes 224 24-bit counters to provide statistical information on the device?s operation. all the counters are cleared by a hardware re set. a maskable interrupt can be gene rated when the counter overflows. counters can also be latched to captur e the state of all registers at once. a predetermined value can also be loaded into a counter. this feature can be us ed to generate an interrupt after a specified number of cells is processe d. counter values are incremented by 1 for every event occurrence and when the count reaches all 1?s, will overflow (to all 0?s). 6.1.1 utopia input i/f counters there are four counters associated wi th the each of the 24 utopia inputs (f rom atm layer to the mt90222/3/4) for a total of 96 counters. these counters record the following information: ? the total number of cells or the total number of user cells received at the utopia input i/f ? the total number of idle cells received at the utopia input i/f, removed or not ? the total number of unassigned cells received at the utopia input i/f, removed or not ? the number of cells having a single or multiple bit erro r in the hec, removed or not but not including the cells where the hec is corrected 6.1.2 transmit tdm i/f counters there are four counters associated with the each of the sixteen transmit tdm li nks for a total of 64 transmit counters. these counters record the following information: ? the total number of cells sent through the tdm link ? the total number of idle/filler cells or the total number of user cells sent through the tdm link ? the total number of stuff cells sent through the tdm link ? the total number of icp cells sent through the tdm link 6.1.3 receive tdm i/f counters there are four counters associated with each of the sixteen receive tdm links for a total of 64 receive counters. these counters record the following information and are active as soon as the rx tdm port is enabled: ? the total number of cells received through the tdm link or total number of stuff events received on the link ? the total number of idle/filler cells received through the tdm link, with good or bad hec or the total number of user cells ? the total number of icp cells with violation received through the tdm link ? the total number of cells with wrong hec, discarded or not, received through the tdm link but not including the cells where the hec is corrected note that the number of stuff cells is in cluded in the total number of user cells.
mt90222/3/4 data sheet 67 zarlink semiconductor inc. 6.1.4 access to the counters accessing (read) counters is a three step operation. firs t, the desired counter must be selected by writing to the select counter register (0x0432) . second, the read command (?0x00x101?) is written to the counter transfer command (0x040f) register. this command causes the current th ree byte count value to be copied from the specified counter to the two 16 bit-wide counter upper byte (0x0430) and counter bytes 2 and 1 register (0x0431) registers (note that this value is unchanged until a nother counter read command is issued). lastly, the counter upper byte (0x0430) and counter bytes 2 and 1 register (0x0431) registers are read to obtain the three byte count value of the selected counter. pre-loading (write) a counter is also a three step function. first, the three byte pre-load value is written to the two 16 bit-wide counter upper byte (0x0430) and counter bytes 2 and 1 register (0x0431) registers. second, the identification of th e counter to be pre-loade d is written to the select counter register (0x0432) . lastly, the write command (?0x00x001?) is written to the counter transfer command (0x040f) register. the irq enable bit of a counter is set, or reset, by sele cting the counter and writing to the appropriate bit of the counter transfer command (0x040f) register. the value?0x001010? enables the counter irq and ?xxx00010? disables (masks) it. 6.1.5 latching counter mode an additional mode of operation is available in the counte r block where the values of the counters are transferred, all at the same time, to a series of internal register s. the transfer can be initia ted automatically based on an input signal or following a transfer command under software contro l. the transfer mode can be disabled to utilize the counters in the same method as in the mt90220/221. when the source for the latch command is from the dedicate d input pin, the user has t he option to use directly this signal as a latch command or to divide the incomi ng signal by 8000 before generat ing the latch command (for example, using the 8 khz f0 fr ame pulse signal to create 1 second intervals). bits in the counter transfer command (0x040f) register are defined to s upport these new features. the counters are 24 bits wide when operated as in the mt90220/221 (i.e., without the latching option) and are 16 bits wide when the latching feature is e nabled. after each latch signal, all the counters are reset to 0 in order to report the number of events between two latch commands. before the latching mode is enabled, the counters may be lo aded (or reset), but the software should not write to the counters after the latching mode is enabled. note: the content of the counter for all cells in the utopia transmit block for t he ima group 7 is not reset by the latch command when the counters are operating in latch mode. the counter will cont ain a cumulative count of the atm cells that were received on the corresponding utopia port address. this counter is defined by the value 0x0177 in the select counter register (0x0432) .
mt90222/3/4 data sheet 68 zarlink semiconductor inc. figure 18 - irq re gister hierarchy 6.2 interrupt block the mt90222/3/4 can generate interrupts from many sour ces. all interrupt sources can be enabled or disabled. write action is required to clear t he source of interrupt. interrupts are grouped on a per link basis, with six sub-categories for each link and two special types for the im a group configuration. these special interrupts are only present in the link 0 irq stat us register. refer to figure 18 for a repres entation of the interrupt register hierarchy. 6.2.1 irq master status and irq master enable registers there is a irq master status (0x0455) register that reports inte rrupts generated by any event on any of the links. each bit of this register corresponds to a link. a ?1? in a bit position indicates that the associated link is reporting an interrupt condition. for each bit in the irq master status (0x0455) register, there is a corresponding bit in the irq master enable (0x0433) register. when any irq source is active and the corresponding enable bit is ?1?, then the irq pin will go low (active). s t a t u s group counters utopia ima link 15 link 14 link 13 ....... link 3 link 2 link 1 link 0 link 15 irq pin link 0 lcd lif lods iv new rx icp tc link overflow status counters counters 4 tx 4 rx s t a t u s counters 4 utopia s t a t u s s t a t u s ready bit/icp cell time * note *: these 2 irq signals are only present in irq link status register (0x0435) for link 0. 1 utopia rx fifo overflow ima group overflow ima overflow 1 set of registers 8 registers counters 4 utopia 1 utopia rx fifo overflow frame pulse transfer done tx icp cell handler register s t a t u s s t a t u s 16 x irq link registers 1 x irq master registers ima grp cntrs * e n a b l e e n a b l e e n a b l e e n a b l e 0 11 0 7 0 7 overflow in icp pre-proc end of lcd end of lif end of lods 0 7
mt90222/3/4 data sheet 69 zarlink semiconductor inc. the irq master status (0x0455) register always repor ts the current state of the sour ce(s) of interrupt. it does not latch the interrupt request(s); it only reports that one or mo re bit(s) in one or more irq link status register(s) is (are) set. the bits that are read as active (?1? value) are cleared when t he source of the interrupt is cleared or when the corresponding bit(s) in the irq link enable (0x0445-0x0454) register(s) is (are) set to 0. writing to or reading from the irq master status (0x0455) register has no effect on the level of the interrupt pin. 6.2.2 irq link status and irq link enable registers there are sixteen irq link status (0x0435-0x0444) and sixteen irq link enable (0x0445-0x0454) registers; one of each per link. the following six types of interrupts ar e reported (in the six least significant bits of the irq link status registers) for each link: ? bit 11 latched: reports the end of an lods (link is out of delay synchronization) condition on a rx tdm link ? bit 10 latched: reports the end of an lif (loss of ima frame) condition on a rx tdm link ? bit 9 latched: reports the end of an lcd (loss of cell delineation) condition on a rx tdm link ? bit 6 latched: reports an overflow in the icp pre-processing ram ? bit 5 latched: reports that an icp cell with changes was received on a rx tdm lin. ? bit 4 latched: reports an iv (icp cell violation) condition on a rx tdm link ? bit 3 latched: reports an lods (link is out of delay synchronization) condition on a rx tdm link ? bit 2 latched: reports an lif (loss of ima frame) condition on a rx tdm link ? bit 1 latched: reports an lcd (loss of ce ll delineation) condition on a rx tdm link bit 0 (lsb) is a status bit. it repor ts an interrupt for an overflow conditio n in one or more of the 24 counters associated with the link. it is also used to report an over flow condition in the utopia rx fifo associated with a tdm link in tc mode. if enabled, a count er generates an interrupt request when it overflows (i.e starts over from 0 after reaching the maximum counter value). see 6.1 counter block paragraph for more details on the operation of the counters. these 13 sources of ov erflow can be identified through the irq link fifo overflow and irq utopia fifo overflow status registers. reading the irq link status (0x0435-0x0444) register does not clear the source of interrupt. the bit 0 status is reset by any one of the following procedures: ? disabling (masking) the irq for this specific counter ? clearing the overflow status bit in the irq link tc overflow status (0x0410-0x041f) registers ? disabling the interrupt in the irq link tc overflow enable (0x0434) or in the corresponding link (in tc mode) counter registers bits 1 to 6 and 9 to 11 of the irq link status (0x0435-0x0444) registers are latches that report the source of an interrupt. writing a ?0? these bits will reset the status bit (w ill reset the latch). writing ?0? to bit 0 has no effect on the status bit. writing a ?1? has no effect on the bits 0 to 6 and 9 to 11 of the irq link status (0x0435-0x0444) register. each one of these 10 interrupt sources can be enabled by writing a ?1? in the irq link enable (0x0445-0x0454) registers to the bi t corresponding to the interrupt source. in some situations, an interrupt source can be masked as par t of an interrupt service routine. this makes it possible to detect further interrupts of higher priority. for example, if an interrupt for a counter is received, the source of the interrupt can be masked by writing 0 to the correspon ding bit and then starting a separ ate process outside of the interrupt service routine. the independent process w ould read, reload and re-enable the counter to produce
mt90222/3/4 data sheet 70 zarlink semiconductor inc. another interrupt service request, if necessary. at the end of this process, the enable bit in the irq link enable (0x0445-0x0454) register would be set to ?1? to det ect any future interrupt requests. 6.2.2.1 bit 8 and 7 of irq link 0 status and irq link 0 enable registers bits 8 and 7 of the irq link 0 status (0x0435) register have a special operation. bit 8 reports an overflow condition in any of the counters or utopia rx fifo s associated with one of the eight ima groups. refer to irq ima group overflow status (0x0457) and irq ima group overflow enable (0x040b) registers for more details. bit 8 is a stat us bit and is cleared by disabling the ir q for this specific counter or disabling (masking) the fifo overflow condition by writing to the rx utopia ima group fifo overflow irq enable (0x040c) register. bit 7 is used to report the following two event types: ? the icp cell internal transfer is complete (reported by any ima group tx icp cell ready bit) ? the end of an ima frame on the reference link of an ima group the second type of event assists in implementing the soft ware counter required to veri fy that group status and control field information is sent fo r at least 2 consecutive ima frames. the sixteen interrupt sources are enabl ed independently by writing to the tx icp cell interrupt enable (0x0088) register and the tx ima frame interrupt enable (0x0089) register. note that both interrupts from the ima frame and the icp cell internal transfer have to be enabled for an interrupt to be generated. there is also an associated control/status register ( tx icp cell handler (0x0086) register) that reports the interrupt source and the state of the transfer of an icp cell or the occurrence of the end of an ima frame. the frame status bits are cleared by writing 0 to the bit. the ready bit is set to 1 when the transfer is complete. bit 6 is a latched bit in the irq link 0 status (0x0435) register and is cleared by overwriting it with 0. each of these two interrupt sources can be masked by writi ng a ?1? to the bit corresponding to the interrupt source in the irq link 0 enable (0x0445) register. 6.2.3 irq link tc overflow status registers the irq link tc overflow stat us registers (0x0410 - 0x041f) report the overflow condition from any of the counters associated with the tx tdm link, the rx tdm link or the tx utopia i/f. they also report the overflow condition from the level of the utopia rx fifo when t he link is used in tc mode. the 13 interrupt sources are organized as follows: ? 1 bit (12) for the rx utopia fifo for tc mode overflow ? 4 bits (11:8) for the utopia input counters ? 4 bits (7:4) for the tx tdm link counters ? 4 bits (3:0) for the rx tdm link counters 6.2.4 irq ima group overflow status and enable registers the sources of ima group overflow conditions are organized in two levels of registers: ? eight low level, 5-bit registers (one register per ima group) ? one intermediate 4-bit register that is used to report the overflow conditions for each ima group to minimize the number of accesses when identifying the source of an overflow condition the irq ima group overflow status (0x0457) register indicates which one of the eight ima groups is reporting
mt90222/3/4 data sheet 71 zarlink semiconductor inc. an overflow condition. when enabled, the bits in this status register reflect any overflow condition reported by the irq ima overflow status (0x0420-0x0427) registers. the irq ima group overflow enable (0x040b) register is used to enable any overflow conditions for a specific ima group. each of the four bits corr espond to one of the eight ima groups. a value of ?1? enables the report of the overflow condition to the upper irq levels. 6.2.5 irq ima overflow status and rx utop ia ima group fifo over flow enable registers there are five possible sources of overflow cond itions that can be repor ted for each ima group. the irq ima overflow status (0x0420-0x0427) register captures (lat ches) the overflow condition from any of the four counters associated with the utopia tx i/f when the tdm link is used in ima mode. it also latches when an overflow condition occurs in the rx utopia fi fo associated to a tdm link when in ima mode. the status bit is cleared by overwriting it with a 0. readi ng the registers or writing a ?1 ? to these registers will not change the content of the r egisters. a counter ge nerates an interrupt request, if not masked, when the counter overflows (i.e., starts over from 0 after reaching the maximum counte r value - refer to section 6.1 for more details on the operation of the counters). an interrupt request can also be generat ed, if not masked, when an overflow condition is detected in the utopia rx fifo associated with an ima group. there is one enable register used to enable the generation of an interrupt by the overflow condition of the rx utopia fifo associated with an ima group. this is the rx utopia ima group fifo overflow irq enable (0x040c) register. 6.3 microprocessor interface block 6.3.1 access to the various registers since the mt90222/3/4 and microprocessor operate from two different clock sources, access to a mt90222/3/4 register is asynchronous. data is synchronized between the mt90222/3/4 and th e microprocessor using either direct or indirect (synchronize d) methods of access. the direct method is used during a read access whe never data does not change or data changes do not represent any problem. there is no register that clears status bits upon a read access. a write action is always required to clear a status bit. the indirect method is identifi ed with ?s? (indirect and need to synchronize with a ready bit) wher eas the direct access is identified with a ?d? in the regist er tables. 6.3.2 direct access direct access registers can be written or read directly by the microprocessor , without having to use other registers. upon a write access to the mt90222/3/4 in ternal registers, the data is stored in an internal latch and transferred to the destination regist er within 2.5 system clock cycles (50 nsec at 50 mhz). no specific action is required if the microprocessor provides at least 50 nsec (with chip sele ct signal inactive) between 2 consecutive write accesses or between a write and a read back of t he same register. if the microprocessor is faster, then consecutive accesses must be inhibited or wait state(s) introduced (this option is available on most mcus). 6.3.3 indirect access indirect access registers c annot be accessed directly by the microproce ssor. the value is transferred back and forth using registers which hold a copy of the information (data) and internal address of the register. this is required to stabilize the read value. consider for example the transfer of a tx icp cell that requ ires almost 200 system clock cycles. a dedicated ready bit which can optionally generate an interrupt is implemented for this type of transfer.
mt90222/3/4 data sheet 72 zarlink semiconductor inc. accessing any of the 24-bit counters provides another exam ple. a ready bit is implem ented in the counter transfer command register when the transfer is completed. when accessing indirect re gisters specified by the rx delay select (0x02aa) or rx delay link number (0x0286) registers, the value in the indirect registers can be read when the writ e to the selection regist er is effectively done (i.e., 2.5 system clock cycles afte r the write cycle is completed). th ere is no additional delay required. 6.3.4 clearing of status bits the status bits will remain set until cl eared by a specific write action from t he microprocessor. status bits are cleared by overwriting a zero to the correspondi ng position in the source register. each input status register has a related interrupt enable register. when enabled, setting a bit in the interrupt enabl e register causes an interrupt to occur in the corresponding stat us register bit. 6.3.4.1 toggle bit some registers include a toggle bit. toggle bits are used to i ndicate a write action to any internal register has taken place. typically, this bit is toggled 2.5 system clock cycles after performing the write action. to use the toggle bit, its state (either 0 or 1) must be read (polled) and its stat e is changed (toggled) when a write command is completed. this bit is particularly useful w hen the processor clock is much fast er than the mt90222/3/4 system clock. 6.4 cell preprocessor block the icp cell is used in the ima protocol to exchange info rmation to maintain proper operation between the far end and the near end of the ima group. one byte, the sci byte, is used to indicate when there is new information to be processed in the incoming icp cell and it is monitored by the ima software to determine when to process an incoming icp cell. i the normal mode of operati on, the scci byte is monitored and an interrupt is generated whenever the value of the byte had changed. the software has to read most of the bytes of the new icp cell to determine which bytes had changed and take appropriate action. to simplify the monitoring process of the icp cell, the mt 90222/3/4 includes an option to compare, on a per byte by byte basis, the most recent incoming cell placed in the rx icp cell buffer with the previous cell written in the same buffer. the cells that are placed in the rx cell buffe r are selected based on the criteria specified in the rx cell type ram (0x0100-0x0101) registers. another option can be selected wh ere bytes 8, 52 and 53 are not compared and are not reported. (byte 8 c ontains the ima frame sequence number. it is used for the ima frame state machine and is not used by the link or group state machines . bytes 52 and 53 contain the crc-10 and are not required by the user.) the rx cell processo r can be enabled on a per link basis. when the new byte is different, a copy of the new byte along with the byte number is put into a dedicated preprocessor fifo, accessible via the processed rx cell link fifo (0x0140 - 0x014f) registers. there is one preprocessor fifo (circular buffer) of 64 entries per rx li nk. each fifo entry is 16 bits wide and the mt90222/3/4 increments automatically the internal pointer to point to the next entry for the next read access. the least significant byte (bits 7 to 0) contains the newly received byte that wa s found to be different. bits 13 to 8 contain the byte position in the atm cell. the numbering scheme goes from byte #1 to byte #53. the bit 14 is used as a flag to indicate the last byte that was found to be different in the newly rece ived atm cell that was put in the rx cell buffer. bit 15 is used to indicate if there are more bytes in the fifo. a valu e of "0" indicates the last valid byte (the fifo is empty) and a value of "1" indicates that there are more bytes to be read. see below for a repres entation of a word read from the fifo.
mt90222/3/4 data sheet 73 zarlink semiconductor inc. figure 19 - processed rx cell fifo word format when the pre-processing option is enabled, (using the rx cell processor enable register), the irq normally generated to indicate that a new cell was put in the rx cell buffer is re-defined to indicate that the compare process has been complete and that the bytes that were found to be di fferent are available for the software to access, in the link preprocessor fifo. for each link, the fifo is 64 words deep to accommodate up to 64 preprocessed bytes (bytes that were found to be different). the bytes in the fifo can be from different preprocessed cells. whenever bit 14 of the word read from the fifo is set, i ndicating the last byte of an atm cell, the software has to check the level of bit 15 to determine if there are more bytes to be read from other processed cells on the same link. if there are no more bytes, then the software should start polling the status bit (empty/ not empty) and/or wait for an irq before reading the fifo. to facilitate this task, associated with the rx cell fifos, the processed rx cell link fifo status register (0x107) reports if a fifo is empty or not empty. each bit in the re gister is reflecting the status of one of the sixteen links. when the preprocessing option is not enabled, the rx cell buffers operat e the same way as in the mt90220/221. all 53 bytes from the atm cell are accessible when the preprocessing mode is disabl ed and the preprocessor fifo are not used. 6.5 tdm ring block the tdm ring block is typically used to form ima groups that source their links from more than one mt90222/3/4. all mt90222/3/4 devices in the tdm ring must operate sync hronously, with the same s ystem clock. this system clock needs to be the identical in frequency but not necessarily phase aligned. the tdm ring is located between the tdm serial interface (s/p converters) and the internal transmission control (tc) / ima blocks (see figures 3 and 7). this bus a llows links to be routed from one mt90222/3/4 to other mt90222/3/4s as if the link was internally sourced, limit ed by the mt90224?s link capacity of 16 links (8 links on the MT90223 and 4 links on the mt90222) and the tdm ring capacity of 32 links. operation of the tdm ri ng is programmed via 16 ring tx link (0x0181-0x0190) registers, 16 ring rx link (0x01c0-0x01cf) registers and one ring tx control (0x0180) register. the ring tx control (0x0180) sets which mt90222/3/4 is the master (source of the tdm ring clock) and whether the tdm ring is active (not tri-stated) . there can be only one tdm ring master in a single ring. a link is then placed on the ring by associating it with one available time slot and then retrieved off the ring by referencing the same time slot. see technical note tn90224.1 for more information. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte content from the latest rx cell position in cell for the byte found to be different (number range between 1 and 51) when set, indicates the last byte reported processed rx cell fifo word format for the current processed cell. when clear (0), indicates that the fifo associated with this link is empty (no more bytes to be read)
mt90222/3/4 data sheet 74 zarlink semiconductor inc. 6.6 sram decoding for mt90222/223 the sram decoding block has a feature t hat allows more efficient external sram memory utilization when only 8 or 4 tdm links are used. this is partic ularly pertinent to the MT90223 and mt90222. sram address decoding is based in part on the link number. since the MT90223 and mt90222 use only even numbered links, normal decoding would result in half th e memory not being used. the following method describes how to more fully utilize one external sram component rather than using two external sram components, thus achieving the same differential link delay capacity with reduced board space and cost. with only one external sram physic ally connected, set bit 0 of the sram control (0x0299) register to use two banks of memory. additionally, set bit 8 of the same register to remap sram chip select 1 ( sr_cs_1 ) to the normally unused address line. this combination of using two logical memory banks with chip select remapping will achieve the desired efficient use of a single external sram component. 7.0 register descriptions: throughout the following register descr iptions, it should be noted that only the register s and register bits corresponding to available links are me aningful. registers and register bits corresponding to unavailable links should be masked or otherwise ignored. the mt90224 has links 0:15 . the MT90223 has links 0, 2, 4, 6, 8, 10, 12 and 14. the mt90222 has links 0, 4, 8, and 12. note: for mt90222 groups 0, 1, 2 and 3 should be used. 7.1 register summary address (hex) access type reset value (hex) description 0x0000-0x0007 d 0000 utopia output link address registers 0x0008-0x000b d 0000 utopia output group address registers 0x0010 d 0000 utopia output link phy enable registers 0x0011 d x0000000 00000000 utopia output group phy enable register 0x0012 d 0000 utopia output user defined byte 0x0040-0x0047 d 0000 utopia input link address registers 0x0048-0x004b d 0000 utopia input group address registers 0x0050 d 0000 utopia input link phy enable register 0x0051 d 0000 utopia input group phy enable register 0x0052 d 000x0000 00000000 utopia input control register 0x0053 d 0000 utopia input parity error register 0x0080 d 00000000 1x000000 tx cell ram control register 0x0086 d 00ff tx icp cell handler register 0x0087 d 00ff tx ima frame indication register 0x0088 d 0000 tx icp cell interrupt e nable register 0x0089 d 0000 tx ima frame interrupt enable register table 6 - register summary
mt90222/3/4 data sheet 75 zarlink semiconductor inc. 0x008b-0x0092 d 0101 tx link fifo length definition register 0x0093-0x0096 d 0101 tx ima group fifo length definition register 0x009b d 0000 tx fifo length status register 0x0c0 - 0x0c7 d 0c0c rx link control registers 0x00c8 d 000c loss of delineation register 0x00c9 d 0067 cell delineation register 0x00ca d 0091 ima frame delineation register 0x00cc - 0x00cf d 0101 user defined rx oam label register 0x00d9 d 0000 rx oif status register 0x00da d 0000 rx oif counter clear command register 0x00db d 0000 rx wrong f iller status register 0x00dc d 0000 rx load values/link select register 0x00dd d 0000 rx oam label register 0x00de d 0000 rx link ima id registers 0x00df d 0000 rx icp cell offset register 0x00e0 d 0001 rx link frame sequence number register 0x00e1 d 0000 rx link scci sequence number register 0x00e2 d 0000 rx link oif counter value register 0x00e3 d 0020 rx link id number register 0x00e4 d 0000 rx state register 0x00e5 d 0000 ima frame state machine status register 0x00e6 d 0000 cell delineation status register 0x0100 d 0000 rx cell type ram register 1 0x0101 d 0000 rx cell type ram register 2 0x0102 d 0000 rx cell process enable register 0x0105 d 0000 rx cell buffer increment read pointer register 0x0106 d 0000 rx cell level fifo status register 0x0107 d 0000 processed rx cell link fifo status register 0x0108 d 0000 icp cell ram debug register 0x0140 - 0x014f d 8000 processed rx cell link fifo register 0x0180 d 0000 ring tx control register 0x0181 - 0x0190 d 0000 ring tx link registers 0x01c0 - 0x01cf d 0000 ring rx link registers 0x0201--x0208 d 0000 rx recombiner registers 0x0209 - 0x0210 d 0000 rx reference link control registers address (hex) access type reset value (hex) description table 6 - register summary (continued)
mt90222/3/4 data sheet 76 zarlink semiconductor inc. 0x0219 - 0x021c d 0c0c rx idcr integration registers 0x0280 sync 00000000 1x000000 rx external sram access control register 0x0281 d 0000 increment delay control register 0x0282 d 0000 decrement delay control register 0x0283 d 0000 rx recombiner delay control registers 0x0284 sync 0000 rx external sram read/write data 0x0285 d 0004 rx delay register 0x0286 d 0000 rx delay link number register 0x0287 - 0x028e d 0004 rx guard band/delta delay register 0x0297 sync 0000 rx external sram read/write address 0x0298 sync 0000 rx external sram read/write address 1 0x0299 d 0000 sram control register 0x029a - 0x02a1 d 0000 rx maximum operational delay register 0x02aa d 0000 rx delay select register 0x02ad d 0000 enable recombiner status 0x0300 - 0x0307 d b0 tx group control mode registers 0x0310 - 0x0317 d physical link # tx icp cell offset registers 0x0318 - 0x031f d 0808 tx link control registers 0x0321 - 0x0324 d 3030 tx ima control registers 0x0333 d 0000 tx add link control register 0x0336 - 0x033d d physical link # tx link id registers 0x0345 d 0000 tx link active status register 0x0346 d ffff tx ima mode status register 0x0401 d 0000 utopia input cell counter groups register 0x0402 d 0000 utopia input cell counter links register 0x0403 - 0x0406 d 0c0c tx idcr integration registers 0x040b d 0000 irq ima group overflow enable register 0x040c d 0000 rx utopia ima group fifo overflow irq enable register 0x040e d 0000 general status register 0x040f sync 0080 counter transfer command register 0x0410 - 0x041f d 0000 irq link tc overflow status registers 0x0420 - 0x0427 d 0000 irq ima overflow status registers address (hex) access type reset value (hex) description table 6 - register summary (continued)
mt90222/3/4 data sheet 77 zarlink semiconductor inc. 0x0430 d sync counter upper byte 0x0431 d sync counter bytes 2 and 1 register 0x0432 d sync select counter register 0x0433 d 0000 irq master enable register 0x0434 d 0000 irq link tc overflow enable register 0x0435 - 0x0444 d 0000 irq link status registers 0x0445 - 0x0454 d 0000 irq link enable registers 0x0455 d 0000 irq master status register 0x0457 d 0000 irq ima group overflow status register 0x0500 to 0x05ff d xxxx tx ima icp cell registers 0x0600 - 0x060f d 0000 tdm tx link control register 0x0610 - 0x061f d 0000 tdm tx mapping (timeslots 15:0) register 0x0620 - 0x062f d 0000 tdm tx mapping (timeslots 31:16) register 0x0630 d 0000 txck status register 0x0631 d 0000 rxck status register 0x0632 d 0000 refck status register 0x0633 d 0000 tx sync. status register 0x0634- 0x0635 d 0000 pll reference control register 0x0700 - 0x070f d 0000 tdm rx link control register 0x0710 - 0x071f d 0000 tdm rx mapping (timeslots 15:0) register 0x0720 - 0x072f d 0000 tdm rx mapping (timeslots 31:16) register 0x0730 d 0000 rx sync. status register 0x0741 d 0000 rx automatic atm synchronization register 0x0800 - 0x0bff d xxxx rx ima icp cell address (hex) access type reset value (hex) description table 6 - register summary (continued)
mt90222/3/4 data sheet 78 zarlink semiconductor inc. 7.2 detailed register description address (hex): 0x000-0x007 (8 regs) direct access 1 register per 2 links in non-ima mode. li nk 0 is paired with link 8, link 1 with link 9 and so on. reset value (hex): 0000 bit # type description 15:13 r unused. read all 0?s. 12:8 r/w utopia phy address of link n+8 when in non-ima mode. 7:5 r unused. read all 0?s. 4:0 r/w utopia phy address of link n when in non-ima mode. table 7 - utopia output link address registers address (hex): 0x0008-0x00b (4 regs) direct access 1 reg. per 2 ima groups. ima group 0 is paired with ima group 4, ima group 1 with ima group 5 and so on. for mt90222 only groups 0,1,2 and 3 are used. reset value (hex): 0000 bit # type description 15:13 r unused. read all 0?s. 12:8 r/w utopia phy address of ima group n+4. 7:5 r unused. read all 0?s. 4:0 r/w utopia phy address of ima group n. table 8 - utopia output group address registers address (hex): 0x0010 (1 reg) direct access 1 register to enable the links in non-ima mode. reset value (hex): 0000 bit # type description 15 r/w enable utopia phy address of link 15. a 1 enables the phy port address, non-ima mode. 14 r/w enable utopia phy address of link 14. a 1 enables the phy port address, non-ima mode. ... ... ... 1 r/w enable utopia phy address of link 1. a 1 enables the phy port address, non-ima mode. 0 r/w enable utopia phy address of link 0. a 1 enables the phy port address, non-ima mode. table 9 - utopia output link phy enable registers
mt90222/3/4 data sheet 79 zarlink semiconductor inc. address (hex): 0x0011 (1 reg) direct access 1 register to enab le the ima groups. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (bin): x000000000000000 type description 15 r reserved. 14 r/w reserved. write 0 for normal operation. 13 r/w reserved. write 0 for normal operation. 12 r/w reserved. write 0 for normal operation. 11 r/w 16/8-bit mode selection bit for the rx utopia data bus. when set the rx utopia interface is operating in 8-bit mode, when reset it is operating in 16-bit mode. 10 r/w reserved. write 0 for normal operation. 9 r/w reset utopia rx state machines when set to 1. 8 r/w reserved. write 0 for normal operation. 7 r/w enable utopia phy address of ima gr oup 7. a 1 enables the phy port address. 6 r/w enable utopia phy address of ima gr oup 6. a 1 enables the phy port address. ... ... ... 1 r/w enable utopia phy address of ima gr oup 1. a 1 enables the phy port address. 0 r/w enable utopia phy address of ima gr oup 0. a 1 enables the phy port address. table 10 - utopia output group phy enable register address (hex): 0x0012 (1 reg) direct access 1 register which contains the user defined byte. this byte is inserted into the sixth byte of the header when operating in sixteen-bit mode. reset value (hex): 0000 bit # type description 15:12 r unused. read all 0?s. 11 r/w reserved. write 0 for normal operation 10 r/w reserved. write 0 for normal operation 9 r/w write 0 for normal operation, 1 to tristate parity. 8 r/w parity bit. even parity is selected when this bit is set. odd parity is selected when this bit is cleared. 7:0 r/w user defined byte. this byte is inserted into the sixth byte of the header when cells are being output in 16-bit mode. table 11 - utopia output user defined byte
mt90222/3/4 data sheet 80 zarlink semiconductor inc. address (hex): 0x0040-0x0047 (8 reg) direct access 1 register per 2 links in non-ima mode. link 0 is paired with link 8, link 1 with link 9 and so on reset value (hex): 0000 bit # type description 15:13 r unused. read all 0?s. 12:8 r/w utopia phy address of link n+8 when in non-ima mode. 7:5 r unused. read all 0?s. 4:0 r/w utopia phy address of link n when in non-ima mode. table 12 - utopia input link address registers address (hex): 0x0048-0x004b (4 reg) direct access 1 register per 2 ima groups. ima gro up 0 is paired with ima group 4, ima group 1 with ima group 5 and so on. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:13 r unused. read all 0?s. 12:8 r/w utopia phy address of ima group n+4. 7:5 r unused. read all 0?s. 4:0 r/w utopia phy address of ima group n. table 13 - utopia input group address registers address (hex): 0x0050 (1 reg) direct access 1 register to enab le the links in non-ima mode. reset value (hex): 0000 bit # type description 15 r/w enable utopia phy address of link 15. a 1 enables the phy port address, non-ima mode. 14 r/w enable utopia phy address of link 14. a 1 enables the phy port address, non-ima mode. ... ... ... 1 r/w enable utopia phy address of link 1. a 1 enables the phy port address, non-ima mode. 0 r/w enable utopia phy address of link 0. a 1 enables the phy port address, non-ima mode. table 14 - utopia input link phy enable register
mt90222/3/4 data sheet 81 zarlink semiconductor inc. address (hex): 0x0051 (1 reg) direct access 1 register to enab le the ima groups. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:12 r unused. reads all 0?s. 11:8 r/w reserved. write all 0?s for normal operation. 7 r/w enable utopia phy address of ima group 7. a 1 enables the phy port address. 6 r/w enable utopia phy address of ima group 6. a 1 enables the phy port address. ... ... ... 1 r/w enable utopia phy address of ima group 1. a 1 enables the phy port address. 0 r/w enable utopia phy address of ima group 0. a 1 enables the phy port address. table 15 - utopia input group phy enable register address (hex): 0x0052 (1 reg) direct access 1 register for all the utopia input ports. reset value (hex): 000x000000000000 bit # type description 15:14 r unused. read all 0?s 13 r reserved. write 0 for normal operation 12 r/w parity bit. the incoming parity bit is odd parity when 0, even parity when 1. 11 r/w reserved. write 0 for normal operation 10 r/w reserved. write 0 for normal operation 9 r/w utopia loopback mode indicator. when set the tx utopia will accept cells and loop these back to the rx utopia interfac e. the rx utopia interface w ill then output these cells. 8 r/w reserved. write 0 for normal operation 7 r/w selects between 16- and 8-bit mode for the utopia bus. a 0 selects a 16-bit wide bus and a 1 selects an 8-bit wide bus. 6 r/w a 1 resets the state of the input utop ia controller. write 0 for normal operation. 5 r/w reserved. write 0 for normal operation. 4 r/w unassigned cell filter. a 1 signifies that the unassigned 1 cells coming from the atm layer will be discarded. the unassigned/idle cell counter is incremented for each cell discarded. 3 r/w idle cell filter. a 1 signifies that the idle 2 cells coming from the atm layer will be discarded. the unassigned/idle cell counter is incremented for each cell discarded. 2 r/w atm forum polynomial. a 1 disables the add ition of the atm forum polynomial calculation on the hec calculated as per i.432. a 0 means t hat the coset value is included in the hec value. table 16 - utopia input control register
mt90222/3/4 data sheet 82 zarlink semiconductor inc. 1:0 r/w hec verification. 11: enable hec error correction if 1 bit is wr ong, discard cell if more than 1 bit are wrong. 10: discard cell if hec is wrong, no hec correction. 01: enable hec error correction if 1 bit is wrong , no correction if more than 1 bit wrong, cell is not discarded if hec is wrong. 00: no verification of hec. 1. unassigned cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0. 2. idle cells have a fixed header corresponding to 00000000 00000000 00000000 00000001 address (hex): 0x0053 (1 reg) direct access 1 register to contain information about parity errors on the tx utopia data bus. reset value (hex): 0000 bit # type description 15 rol indicates that the parity error counter has roll ed-over. this is a sticky bit which is set by the hardware and reset by the user (by writing ?0? to this bit). 14 rol indicates that at least one parity error has occu rred since this register was reset. this is a sticky bit which is set by the hardware and rese t by the user (by writing ?0? to this bit. 13 w when written with a 1 the internal tx utopia parity error counter value will be transferred to the lower 12 bits of this regist er. when written with ?0?, no transfer is done. 13 r reading a 1 in this register indicates that the tx utopia parity error counter has been updated. reading a 0 indicates that the register is not updated yet. 12 r/w when this bit is set the tx utopia parity error counter will be reset. when this bit is reset the tx utopia parity error counter will operate normally 11:0 r tx utopia parity error counter. these bits contain the value of the tx utopia parity error counter. the counter must be l oaded into the register using bit 13. table 17 - utopia input parity error register address (hex): 0x0080 (1 reg) direct access used for initialization of the internal tx internal cell ram (filler, idle cells etc.) reset value (bin): 000000001x000000 bit # type description 15:8 r unused. read all 0?s. 7 r status bit. goes to 0 during initialization and returns to 1 on completion of initialization. 6 r/w write 1 to this bit for normal operation. write 0 in conjunction with bit 0 to initialize the tx cell ram; otherwise, write 1. table 18 - tx cell ram control register address (hex): 0x0052 (1 reg) direct access 1 register for all the utopia input ports. reset value (hex): 000x000000000000 bit # type description table 16 - utopia input control register (continued)
mt90222/3/4 data sheet 83 zarlink semiconductor inc. 5 r/w reserved. write 0 for normal operation. 4:1 r/w reserved. write 0?s for normal operation. 0 r/w reserved. write 0 to initialize the internal cell ram. address (hex): 0x0086 (1 reg) direct access controls the transfer of tx icp cel ls. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 00ff bit # type description 15:8 r unused. read all 0?s. 7 r/w write 0 to initiate the transfer of the tx icp cell from the tx icp cell memory to the internal memory for the ima group 7. the bit r eads ?0? until the transfer is complete, the bit reads ?1?. write a ?1? has no effect. 6 r/w write 0 to initiate the transfer of the tx icp cell from the tx icp cell memory to the internal memory for the ima group 6. the bit r eads ?0? until the transfer is complete, the bit reads ?1?. write a ?1? has no effect. ... ... ... 1 r/w write 0 to initiate the transfer of the tx icp cell from the tx icp cell memory to the internal memory for the ima group 1. the bit r eads ?0? until the transfer is complete, the bit reads ?1?. write a ?1? has no effect. 0 r/w write 0 to initiate the transfer of the tx icp cell from the tx icp cell memory to the internal memory for the ima group 0. the bit r eads ?0? until the transfer is complete, the bit reads ?1?. write a ?1? has no effect. table 19 - tx icp cell handler register address (hex): 0x0087 (1 reg) direct access indicates the begi nning of the frame on the ref link. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 00ff bit # type description 15:8 r unused. read all 0?s. 7 r/w write 0 to detect when an icp cell is sent on the reference link for the ima group 7. the bit reads ?0? until an icp cell is sent on the ref. link, then it reads ?1?. write ?1? has no effect. table 20 - tx ima frame indication register address (hex): 0x0080 (1 reg) direct access used for initialization of the internal tx internal cell ram (filler, idle cells etc.) reset value (bin): 000000001x000000 bit # type description table 18 - tx cell ram control register (continued)
mt90222/3/4 data sheet 84 zarlink semiconductor inc. 6 r/w write 0 to detect when an icp cell is sent on the reference link for the ima group 6. the bit reads ?0? until an icp cell is sent on the ref. link, then it reads ?1?. write ?1? has no effect. ... ... ... 1 r/w write 0 to detect when an icp cell is sent on the reference link for the ima group 1. the bit reads ?0? until an icp cell is sent on the ref. link, then it reads ?1?. write ?1? has no effect. 0 r/w write 0 to detect when an icp cell is sent on the reference link for the ima group 0. the bit reads ?0? until an icp cell is sent on the ref. link, then it reads ?1?. write ?1? has no effect. address (hex): 0x0088 (1 reg) direct access interrupt enable register for th e tx icp handler register.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7 r/w write 1 will enable the generation of an interr upt when the transfer of the tx icp cell for the ima group 7 is completed. a 0 will inhibit the generatio n of an interrupt. 6 r/w write 1 will enable the generation of an interr upt when the transfer of the tx icp cell for the ima group 6 is completed. a 0 will inhibit the generatio n of an interrupt. ... ... .... 1 r/w write 1 will enable the generation of an interr upt when the transfer of the tx icp cell for the ima group 1 is completed. a 0 will inhibit the generatio n of an interrupt. 0 r/w write 1 will enable the generation of an interr upt when the transfer of the tx icp cell for the ima group 0 is completed. a 0 will inhibit the generatio n of an interrupt. table 21 - tx icp cell interrupt enable register address (hex): 0x0087 (1 reg) direct access indicates the begi nning of the frame on the ref link. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 00ff bit # type description table 20 - tx ima frame indication register (continued)
mt90222/3/4 data sheet 85 zarlink semiconductor inc. address (hex): 0x0089 (1 reg) direct access interrupt enable register for th e tx icp handler register.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7 r/w write 1 will enable the generation of an interr upt from the frame indication for ima group 7. a 0 will inhibit the generation of an interrupt. 6 r/w write 1 will enable the generation of an interr upt from the frame indication for ima group 6. a 0 will inhibit the generation of an interrupt. ... ... .... 1 r/w write 1 will enable the generation of an interr upt from the frame indication for ima group 1. a 0 will inhibit the generation of an interrupt. 0 r/w write 1 will enable the generation of an interr upt from the frame indication for ima group 0. a 0 will inhibit the generation of an interrupt. table 22 - tx ima frame interrupt enable register address (hex): 0x008b-0x0092 (8 reg) direct access 1 register per 2 links. link 0 is paired with link 8, link 1 is paired with link 9 and so on. reset value (hex): 0101 bit # type description 15:12 r unused. read 0?s. 11:8 r/w tx fifo length link n+8. 7:4 r/w reserved. write 0?s for normal operation. 3:0 r/w tx fifo length link n. table 23 - tx link fifo length definition register address (hex): 0x0093-0x0096 (4 reg) direct access 1 register per 2 ima groups. gr oup 0 is paired with group 4, group 1 is paired with group 5 and so on. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0101 bit # type description 15:12 r/w unused. read 0?s. 11:8 r/w tx fifo length ima group n+4. 7:4 r/w reserved. write 0?s for normal operation. 3:0 r/w tx fifo length ima group n table 24 - tx ima group fifo length definition register
mt90222/3/4 data sheet 86 zarlink semiconductor inc. address (hex): 0x009b (1 reg) direct access reset value (hex): 0000 bit # type description 15:7 r unused. read 0?s. 6:0 r 6:0 contains fifo length free cells 4:0 contains fifo length of ima groups and links 5:0 w selects fifo: 000000 - 001111: selects link fifo 010000 - 010111: selects ima fifo 011000: selects free cell fifo 100000 - 101111: selects icp cell modifier length link fifo table 25 - tx fifo length status register address (hex): 0x00c0 - 0x00c7 (8 reg) direct access 1 register per 2 links. link 0 is pair ed with link 8, link 1 with link 9 and so on. reset value (hex): 0c0c bit # type description 15 r/w a value of 1 means that al l cells are counted for the link n+ 8. a value of 0 means that all stuff cells are counted for the link n+8. 14 r/w a value of 1 enables the ima mode for the link n+8. a value of 0 enables the non-ima mode for the link n+8. 13 r/w a value of 1 enables the descrambling of the cell for the link n+8 12 r/w when set to 1, count all user cells for link n+8, when cleared to 0, count filler /idle/unassigned cells for link n+8. 11 r/w a value of 1 means that the unassigned a nd idle cells are discarded upon reception for the link n+8. 10 r/w a value of 1 enables the di scard option of the cells with wrong hec. a value of 0 will disables the discard option, all the cells will be wri tten to the receive buffer. 9 r/w a value of 1 signifies that the atm forum polynomial value (coset) is not to be added to the hec before the verification. a value of 0 me ans that the hec is calculated and compared (i.e., including the coset). 8 r/w a value of 1 enables the correction of the ce lls with a wrong hec. a value of 0 disable the correction of the hec. 7 r/w a value of 1 means that all cells are counted fo r the link n. a value of 0 means that all stuff cells are counted for the link n. 6 r/w a value of 1 enables the ima mode for this link. a value of 0 enables the non-ima mode for the link n. 5 r/w a value of 1 enables the descrambling of the cell for the link n 4 r/w when set to 1, count al l user cells for link n, when cleared to 0, count filler /idle/unassigned cells for link n. table 26 - rx link control registers
mt90222/3/4 data sheet 87 zarlink semiconductor inc. 3 r/w a value of 1 means that the unassigned and idle cells are discarded upon reception for the link n. 2 r/w a value of 1 enables the discard option of the cells with wrong hec. a value of 0 will disables the discard option, all the cells will be wri tten to the receive buffer. 1 r/w a value of 1signifies that the atm forum po lynomial value (coset) is not to be added to the hec before the verification. a value of 0 means that the hec as per atm forum is calculated and compared (i.e., including the coset). 0 r/w a value of 1 enables the correction of the ce lls with a wrong hec. a value of 0 disable the correction of the hec. address (hex): 0x00c8 (1 reg) direct access 1 reg. for all 16 cel l delineation state machines. reset value (hex): 000c bit # type description 15:8 r unused. read all 0?s. 7:0 r/w contains the number of consecutive cell pe riods that the cd circuit will count before the incoming atm cell stream to be considered in lcd state. each count will be done on a cell by cell basis. the value of this regist er is multiplied by 2 before being loaded in the internal counter. (the internal count er value can be from 2 to 510). note that a value of 0 is not allowed as an lcd condition would be generated. table 27 - loss of delineation register address (hex): 0x00c9 (1 reg) direct access 1 register for all 16 cell delineation state machines reset value (hex): 0067 bit # type description 15:8 r unused, read all 0?s. 7:4 r/w delta parameter value for the cell delinea tion register. the number of consecutive cells with correct hec to leave the presync state to go to the sync state. the default value is 6. 3:0 r/w alpha parameter value for the cell delineation register. the number of consecutive cells with incorrect hec to leave the sync state to go to the hunt state. the default value is 7. table 28 - cell delineation register address (hex): 0x00c0 - 0x00c7 (8 reg) direct access 1 register per 2 links. link 0 is pair ed with link 8, link 1 with link 9 and so on. reset value (hex): 0c0c bit # type description table 26 - rx link control registers (continued)
mt90222/3/4 data sheet 88 zarlink semiconductor inc. address (hex): 0x00ca (1 reg) direct access 1 reg. for all 8 ima frame state machines. reset value (hex): 0091 bit # type description 15:9 r unused. read all 0?s. 8 r/w reserved. write 0 for normal operation. 7:6 r/w alpha parameter value for the ima fram e delineation.state machine. the number of consecutive invalid icp cells to leave the ima sync state to go to the ima hunt state.the default value is 2. 5:3 r/w beta parameter value for the cell delineation.state machine. the number of consecutive errored icp cells to leave the ima sync state to go to the ima hunt state. the default value is 2. 2:0 r/w gamma parameter value for the frame delineation state machine. the number of consecutive valid icp cells to leave the ima presync state to go to the ima sync state. the default value is 1. table 29 - ima frame delineation register address (hex): 0x00cc - 0x00cf (4 reg) direct access 1 reg. per 2 ima groups. ima group 0 is paired with ima group 4 and so on.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0101 bit # type description 15:8 r/w rx oam label for ima group n+4. 7:0 r/w rx oam label for ima group n. table 30 - user defined rx oam label register address (hex): 0x00d9 (1 reg) direct access 1 register for the 16 rx links. reset value (hex): 0000 bit # type description 15 r/w an oif state was detected on the ph ysical link 15. clear ed by writing a 0. 14 r/w an oif state was detected on the ph ysical link 14. clear ed by writing a 0. ... ... ... 1 r/w an oif state was detected on the ph ysical link 1. cleared by writing a 0. 0 r/w an oif state was detected on the ph ysical link 0. cleared by writing a 0. table 31 - rx oif status register
mt90222/3/4 data sheet 89 zarlink semiconductor inc. address (hex): 0x00da (1 reg) direct access 1 register for the 16 rx links. reset value (hex): 0000 bit # type description 15 r/w write a 0 to clear the oi f counter for physical link 15. 14 r/w write a 0 to clear the oi f counter for physical link 14. ... ... ... 1 r/w write a 0 to clear the oif counter for physical link 1. 0 r/w write a 0 to clear the oif counter for physical link 0. table 32 - rx oif counter clear command register address (hex): 0x00db (1 reg) direct access 1 register for the 16 rx links. reset value (hex): 0000 bit # type description 15 r/w set to 1 to indicate th at at least 1 filler cell with a wrong crc was received on link 15. the bit is reset by writing 0 to it. 14 r/w set to 1 to indicate th at at least 1 filler cell with a wrong crc was received on link 14. the bit is reset by writing 0 to it. ... ... ... 1 r/w set to 1 to indicate that at least 1 filler cell with a wrong crc was received on link 1. the bit is reset by writing 0 to it. 0 r/w set to 1 to indicate that at least 1 filler cell with a wrong crc was received on link 0. the bit is reset by writing 0 to it. table 33 - rx wrong filler status register address (hex): 0x00dc (1 reg) direct access 1 register to select the link from which to extract the rx icp cells values shown in following registers. reset value (hex): 0000 bit # type description 15:5 r unused. read all 0?s. 4 r this bit toggles after every write to the mt90222/3/4 device. 3:0 r/w selects the rx physical link number to update the values from the rx icp cell. this is typically used when the rx link is enabled but in non-ima mode to collect the values received over the icp cells. table 34 - rx load values/link select register
mt90222/3/4 data sheet 90 zarlink semiconductor inc. address (hex): 0x00dd (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r this register stores the va lue of the rx oam label value extracted from the valid rx icp cell received on the link selected in the rx load values/link select register. table 35 - rx oam label register address (hex): 0x00de (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r this register stores the value of the ima id extracted from the valid rx icp cell received on the link selected in the rx loa d values/link select register. table 36 - rx link ima id registers address (hex): 0x00df (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r defines the icp cell offset of the link sele cted in the rx load values /link select register. the significant bits are used depending on the value of m. m = 256; bits 7-0 are used, m = 128; bits 6-0 are used; m = 64; bits 5-0 are used; m = 32; bits 4-0 are used. table 37 - rx icp cell offset register address (hex): 0x00e0 (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0001 bit # type description 15:8 r unused. read all 0?s. 7:0 r this register repo rts the ima frame sequence number as reported in the last received valid icp cell of the selected link. table 38 - rx link frame sequence number register
mt90222/3/4 data sheet 91 zarlink semiconductor inc. address (hex): 0x00e1 (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r this register repo rts the scci sequence number as reported in the last received valid icp cell of the link selected in the rx load values/link select register. table 39 - rx link scci sequence number register address (hex): 0x00e2 (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r content of the oif counter for the link selected in the rx load values/link select register. table 40 - rx link oif counter value register address (hex): 0x00e3 (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0020 bit # type description 15:8 r unused. read all 0?s. 7 r lif state of the link selected in th e rx load values/link select register. 6 r lcd state of the link selected in the rx load values/link select register. 5 r a value of 1 means that the link selected in the rx load values/link select register is a reference link for his ima group. 4:0 r these bits report the link id number fo r the link selected in the rx load values/link select register. table 41 - rx link id number register
mt90222/3/4 data sheet 92 zarlink semiconductor inc. address (hex): 0x00e4 (1 reg) direct access the value is updated on completion of the write action in the rx load values register. reset value (hex): 0000 bit # type description 15:6 r unused. read all 0?s. 5:4 r frame length (value of m) of the link selected in the rx load values/link select register. 3:2 r ima frame state: 00: hunt 01: presync 10: sync. 11: stuffed frame event. 1:0 r cell delineation state: 00: hunt 01: presync 10: sync. 11: unused. table 42 - rx state register address (hex): 0x00e5 (1 reg) direct access 1 register for all links. reset value (hex): 0000 bit # type description 15 r a 1 indicates that the ima frame state mach ine (ifsm) for the link 15 is in synchronized state. a 0 indicates that the if sm for the link 15 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the ifsm. 14 r a 1 indicates that the ima frame state mach ine (ifsm) for the link 14 is in synchronized state. a 0 indicates that the if sm for the link 14 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the ifsm. ... ... ... 1 r a 1 indicates that the ima frame state mach ine (ifsm) for the link 1 is in synchronized state. a 0 indicates that the ifsm for the link 1 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the ifsm. 0 r a 1 indicates that the ima frame state mach ine (ifsm) for the link 0 is in synchronized state. a 0 indicates that the ifsm for the link 0 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the ifsm. table 43 - ima frame state machine status register
mt90222/3/4 data sheet 93 zarlink semiconductor inc. address (hex): 0x00e6 (1 reg) direct access 1 register for all links. reset value (hex): 0000 bit # type description 15 r a 1 indicates that the cell delineation state machine (cd) for the link 15 is in synchronized state. a 0 indicate s that the cd for the link 15 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the cd. 14 r a 1 indicates that the cell delineation state machine (cd) for the link 14 is in synchronized state. a 0 indicate s that the cd for the link 14 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the cd. ... ... ... 1 r a 1 indicates that the cell delineation state machine (cd) for the link 1 is in synchronized state. a 0 indicates that the cd for the link 1 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the cd. 0 r a 1 indicates that the cell delineation state machine (cd) for the link 0 is in synchronized state. a 0 indicates that the cd for the link 0 is in not in the synchronized state. this bit is not latched and is reflecting the current state of the cd. table 44 - cell delineation status register address (hex): 0x0100 (1 reg) direct access access for rx link 7, 6, 5, 4, 3, 2, 1, 0 reset value (hex): 0000 bit # type description 15:14 r/w these 2 bits select the type of cells stor ed in the rx icp cell buffer for physical link 7 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 13:12 r/w these 2 bits select the type of cells stor ed in the rx icp cell buffer for physical link 6. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. ... ... ... 3:2 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 1. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 1:0 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 0. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. table 45 - rx cell type ram register 1
mt90222/3/4 data sheet 94 zarlink semiconductor inc. address (hex): 0x0101 (1 reg) direct access access for rx link 15, 14, 13, 12, 11, 10, 9, 8. reset value (hex): 0000 bit # type description 15:14 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 15. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 13:12 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 14. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. ... ... ... 3:2 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 9. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 1:0 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 8. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. table 46 - rx cell type ram register 2 address (hex): 0x0102 (1 reg) direct access 1 bit per rx links. reset value (hex): 0000 bit # type description 15:0 r/w when a bit is set to 1, the corresponding new cell placed in the rx icp cell fifo is pre-processed to determine which byte(s) were changed when compared to the previous cell placed in the rx icp buffer. when a bit is set to 0, it means that no pre-processing is to take place. table 47 - rx cell process enable register
mt90222/3/4 data sheet 95 zarlink semiconductor inc. address (hex): 0x0105 (1 reg) direct access 1 reg. for all 16 rx link fifo. reset value (hex): 0000 bit # type description 15 w a value of 1 will increment the position of t he read pointer for the physical link 15. a 0 has no effect. 14 w a value of 1 will increment the position of t he read pointer for the physical link 14. a 0 has no effect. ... ... ... 1 w a value of 1 will increment the position of th e read pointer for the physical link 1. a 0 has no effect. 0 w a value of 1 will increment the position of th e read pointer for the physical link 0. a 0 has no effect. table 48 - rx cell buffer increment read pointer register address (hex): 0x0106 (1 reg) direct access write to bit 3:0 of this register to select the specific link rx icp cell fifo. the value is immediately updated for a read. reset value (hex): 0000 bit # type description 15:6 r unused. read all 0?s. 5:4 r level of rx icp cell fifo. 3:2 r fifo write pointer position 1:0 r fifo read pointer position 3:0 w select link number for fifo status. table 49 - rx cell level fifo status register address (hex): 0x0107 (1 reg) direct access 1 register for all links. reset value (hex): 0000 bit # type description 15 r a 1 indicates that the preprocessing fifo fo r the link 15 is not empty and it contains information to be processed by the software. a 0 indicates that the preprocessing fifo for the link 15 is empty and does not contain any new information. 14 r a 1 indicates that the preprocessing fifo fo r the link 14 is not empty and it contains information to be processed by the software. a 0 indicates that the preprocessing fifo for the link 14 is empty and does not contain any new information. ... ... ... table 50 - processed rx cell link fifo status register
mt90222/3/4 data sheet 96 zarlink semiconductor inc. 1 r a 1 indicates that the preprocessing fifo fo r the link 1 is not empty and it contains information to be processed by the software. a 0 indicates that the preprocessing fifo for the link 1 is empty and does not contain any new information. 0 r a 1 indicates that the preprocessing fifo fo r the link 0 is not empty and it contains information to be processed by the software. a 0 indicates that the preprocessing fifo for the link 0 is empty and does not contain any new information. address (hex): 0x0108 direct access 1 register for debug. reset value (hex): 0000 bit # type description 15:6 r unused. always 0. 5:2 r/w reserved. write 0. 1 r/w 0: compare entire cell 1: compare entire icp cell 0 r/w 0: global debugging disabled. 1: global debugging enabled. table 51 - icp cell ram debug register address (hex): 0x0140 - 0x014f (16 reg) direct access 1 register per rx li nk pre-processed fifo links. reset value (hex): 8000 bit # type description 15 r a 0 indicates that this word contains the last byte in the rx cell processed fifo for the current link. a 1 indicates that there is more bytes that were processed. 14 r a 1 indicates that this word contains the last byte from the rx cell that was processed. a 0 indicates that there is more bytes that were processed from the same cell. 13:8 r cell offset for the byte found to be different (number range between 1 and 53). 7:0 r byte content found to be differ ent from the last received cell. table 52 - processed rx cell link fifo register address (hex): 0x0107 (1 reg) direct access 1 register for all links. reset value (hex): 0000 bit # type description table 50 - processed rx cell link fifo status register (continued)
mt90222/3/4 data sheet 97 zarlink semiconductor inc. address (hex): 0x0180 (1 reg) direct access 1 register for tdm ring tx. reset value (hex): 0000 bit # type description 15:3 r unused. read all 0?s. 2 r/w ring enable: 0: ring is not used and the output tri- state buffers are disabled (high z mode). 1: ring is used and the output tri- state buffers are enabled (active). 1 r/w ring initialization: valid only for ring master 0: run mode. 1: initialization mode. the master device generates empty header bytes to initialize the ring. 0 r/w ring master 0: this device is not the master of the ring. 1: this device is the master of the ri ng (only 1 device can be master on a ring) table 53 - ring tx control register address (hex): 0x0181 - 0x0190 (16 reg) direct access 1 regist er per tx link. reset value (hex): 0000 bit # type description 15:12 r unused. read 0. 11 r/w atm side: 0: normal mode. the external ring is not connected to the icp cell modifier. 1: ring mode. the external ring is connected to the icp cell modifier. 10:6 r/w tx link ring address assi gned to the atm mode switch. 5r/wtdm side: 0: normal mode. the external ring is not connected to the tdm tx interface. 1: ring mode. the external ring is connected to the tdm tx interface. 4:0 r/w tx link ring address assigned to the tdm mode switch. table 54 - ring tx link registers
mt90222/3/4 data sheet 98 zarlink semiconductor inc. address (hex): 0x01c0 - 0x01cf (16 reg) direct access 1 regist er per rx link. reset value (hex): 0000 bit # type description 15:12 r unused. read 0. 11 r/w atm side: 0: normal mode. the external ring is not connected to the rx link group. 1: ring mode. the external ring is connected to the rx link group. 10:6 r/w rx link ring address assigned to the atm mode switch. 5r/wtdm side: 0: normal mode. the external ring is not connected to the tdm rx interface. 1: ring mode. the external ring is connected to the tdm rx interface. 4:0 r/w rx link ring address assigned to the tdm mode switch. table 55 - ring rx link registers address (hex): 0x0201 - 0x0208 (8 reg) direct access 1 register per 2 rx link. link 0 is pa ired with link 8, link 1 with link 9 and so on. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:13 r unused. read all 0?s. 12 r/w recombiner control: 1 to enable the recomb iner and a 0 to disable. this bit works in conjunction with the rx recombiner delay register. 11 r/w reserved: write ?0?. 10:8 r/w these 3 bits specify which ima group the link n+8 belongs to: 000: ima group #0 001: ima group #1 010: ima group #2 011: ima group #3 100: ima group #4 101: ima group #5 110: ima group #6 111: ima group #7 7:5 r/w reserved: write ?0?. 4 r/w recombiner control: 1 to enable the recomb iner and a 0 to disable. this bit works in conjunction with the rx recombiner delay register. 3 r/w reserved: write ?0?. 2:0 r/w these 3 bits specify which ima group the link n belongs to: 000: ima group #0 001: ima group #1 010: ima group #2 011: ima group #3 100: ima group #4 101: ima group #5 110: ima group #6 111: ima group #7 table 56 - rx recombiner registers
mt90222/3/4 data sheet 99 zarlink semiconductor inc. address (hex): 0x0209 - 0x0210 (8 reg) direct access 1 register per ima group. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:9 r unused. read 0. 8:5 r reserved. value may vary . 4 r/w when set to 1, it enables the automatic sele ction of the reference link for the group n. when 0, the link specified in bits 3-0 is used as the reference link. 3:0 r/w these 4 bits specify which physical link is to be used as the reference link for the ima group n. table 57 - rx reference link control registers address (hex): 0x0219 - 0x021c (4 reg) direct access 1 register per 2 im a groups. ima group 0 is paired with ima group 4 and so on. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0c0c bit # type description 15:12 r unused. read all 0?s. 11:8 r/w defines the integrati on period for an ima group n+4 1111: reserved. do not use. 1110: 2 22 clock cycles 1101: 2 21 clock cycles ... 0001: 2 09 clock cycles 0000: 2 08 clock cycles 7:4 r/w reserved. write all 0?s. 3:0 r/w defines the integrati on period for an ima group n 1111: reserved. do not use. 1110: 2 22 clock cycles 1101: 2 21 clock cycles 1100: 2 20 clock cycles (preferred value for e1 with 30 channels) 1011: 2 19 clock cycles (preferred value for t1 with 24 channels) 1010: 2 18 clock cycles 1001: 2 17 clock cycles (preferred value for t1 isdn with 23 channels) 1000: 2 16 clock cycles 0111: 2 15 clock cycles 0110: 2 14 clock cycles 0101: 2 13 clock cycles 0100: 2 12 clock cycles 0011: 2 11 clock cycles 0010: 2 10 clock cycles 0001: 2 09 clock cycles 0000: 2 08 clock cycles table 58 - rx idcr integration registers
mt90222/3/4 data sheet 100 zarlink semiconductor inc. address (hex): 0x0280 (1 reg) synchronized access reset value (bin: 000000001x000000 bit # type description 15:8 r unused. read all 0?s. 7 r upon a write to this register, the bit will go to 0 and will retu rn to 1 when the transfer is completed 6 r toggle bit. changes its state after each rising edge of the bit 7 (ready bit). 5 r/w write 0 to initiate a transfer from the mt90222/3/4 registers to the external ram. write 1 to initiate a transfer from the external ram to the mt90222/3/4 registers. 4:3 r/w unused. read all 0?s 2 r/w reserved. write 0 for normal operation. 1:0 r/w when bit 1 is 1, there is no access to the external ram (no reset or read or write action done). when bit 1 is 0 and bit 0 is 0, then the external ram is initialized. when bit 1 is 0 and bit 0 is 1, then a read or write access to the external ram is performed, as defined by bit 5. table 59 - rx external sram access control register address (hex): 0x0281 (1 reg) direct access used to increment the recombin er delay for an ima group. for mt90222 only groups 0, 1, 2 and 3 are used. the value is in the guardband/delta delay register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7 r/w write a 1 to increment the recombiner delay of ima group #7. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. ... ... ... 2 r/w write a 1 to increment the recombiner delay of ima group #2. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 1 r/w write a 1 to increment the recombiner delay of ima group #1. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 0 r/w write a 1 to increment the recombiner delay of ima group #0. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. table 60 - increment delay control register
mt90222/3/4 data sheet 101 zarlink semiconductor inc. address (hex): 0x0282 (1 reg) direct access used to decrement the recombiner delay for an ima group. the value is in the guardband/delta delay register. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7 r/w write a 1 to decrement the recombiner del ay of ima group #7. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. ... ... ... 2 r/w write a 1 to decrement the recombiner del ay of ima group #2. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 1 r/w write a 1 to decrement the recombiner del ay of ima group #1. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 0 r/w write a 1 to decrement the recombiner del ay of ima group #0. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. table 61 - decrement delay control register address (hex): 0x0283 (1 reg) direct access 1 register for all links. note: the first link of a group shall not be enabled in delayed recombination mode. reset value (hex): 0000 bit # type description 15 r/w a 1 enables the circuitry to wait for the first user cell to be received before adding the link 15 to the recombiner process. a 0 will include the link 15 in the recombiner as soon as it is enabled in the rx recombiner register. 14 r/w a 1 enables the circuitry to wait for the first user cell to be received before adding the link 14 to the recombiner process. a 0 will include the link 14 in the recombiner as soon as it is enabled in the rx recombiner register. ... ... ... 1 r/w a 1 enables the circuitry to wait for the first user cell to be received before adding the link 1 to the recombiner process. a 0 will include t he link 1 in the recombiner as soon as it is enabled in the rx recombiner register. 0 r/w a 1 enables the circuitry to wait for the first user cell to be received before adding the link 0 to the recombiner process. a 0 will include t he link 0 in the recombiner as soon as it is enabled in the rx recombiner register. table 62 - rx recombiner delay control registers
mt90222/3/4 data sheet 102 zarlink semiconductor inc. address (hex): 0x0284 (1 reg) synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s 7:0 r/w rx external sram read/write data register. table 63 - rx external sram read/write data address (hex): 0x0285 (1 reg) direct access this register contains the delay value (in number of cells) selected by the rx delay select register. the value always include the current guardband delay. reset value (hex): 0004 bit # type description 15:11 r sign bits (same value as bit 10) 10:0 r delay value. table 64 - rx delay register address (hex): 0x0286 (1 reg) direct access this register contains the link number associated with the rx delay value register. reset value (hex): 0000 bit # type description 15:9 r unused. read all 0?s 8 r/w reserved. write 0 for normal operation. 7 r/w reserved. write 0 for normal operation. 6 r/w reserved. write 0 for normal operation. 5 r/w set to 1 to enable up access to the external sram, for test purposes. clear to 0 for normal operation. 4 r/w reserved. write 0 for normal operation. 3:0 r number of the physical link associated with the value in the rx delay register. this value is not valid when reading the maximum delay over time. table 65 - rx delay link number register
mt90222/3/4 data sheet 103 zarlink semiconductor inc. address (hex): 0x0287 - 0x028e (8 reg) direct access 1 value for each ima group to use fo r start-up and adding/r emoving delay (value in number of cells). reset value (hex): 0004 bit # type description 15:14 r unused. read all 0?s 13:0 r/w guardband delay value on startup of an im a group or delay value to add or substract when ima group is operational table 66 - rx guardband/delta delay register address (hex): 0x0297 (1 reg) synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 0000 bit # type description 15:4 r unused. read all 0?s 3:0 r/w rx external sram read/write address bit 19:16. table 67 - rx external sram read/write address address (hex): 0x0298 (1 reg) synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 0000 bit # type description 15:0 r/w rx external sram read/write address bit 15:0. table 68 - rx external sram read/write address 1 address (hex): 0x0299 (1 reg) direct access defines the exter nal sram configuration. reset value (hex): 0000 bit # type description 15:9 r unused, read all 0?s 8 r/w write a 1 for MT90223/222 memory optimization 2 . 0 means normal operation. 7 r/w write a 1 to reset the receiver 1 . 0 means no action. 6 r/w write a 1 to reset the transmitter 1 . 0 means no action. 5 r/w write a 1 to reset counters 1 . write 0 for normal operation. 4:3 r/w write 00 for normal operation. table 69 - sram control register
mt90222/3/4 data sheet 104 zarlink semiconductor inc. note 1: a software global reset of the entire mt90222/3/4 component can be achieved by simultaneously writing 1s to bits [7:5]. note 2: setting bit 8 to a value of 1 requires that bit 0 also be set to a value of 1. see section 6.6 2:0 r/w these 3 bits define the size of the external receive memory: 111: reserved 110: reserved 101: 2 banks of 512 k x 8 bits 100: 1 bank of 512 k x 8 bits 011: 2 banks of 128 k x 8 bits 010: 1 bank of 128 k x 8 bits 001: 2 banks of 32 k x 8bits 000: 1 bank of 32 k x 8 bits address (hex): 0x029a - 0x02a1 (8 reg) direct access 1 register per ima group (value in number of cells). for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:14 r unused. read all 0?s. 13:0 r/w value of the maximum operational delay. table 70 - rx maximum operational delay register address (hex): 0x02aa (1 reg) direct access used to initiate an update of the rx delay registers based on the link and delay value to read reset value (hex): 0000 bit # type description 15:9 r unused. read all 0?s. 8:7 r/w write 00 for normal operation 6 r/w writing a 1 will reset the value of the maxi mum delay over time r egister for the selected ima group (see bits 2:0). 5:4 r/w delay register: 11: maximum delay over time (see bits 2:0) 10: current maximum delay for an ima group (see bits 2:0) 01: current minimum delay fo r an ima group (see bits 2:0) 00: current delay for a link (see bits 3:0) 3:0 r/w bits 3:0 are used to specify the physical link number. bits 2:0 are used to specify the physical ima group number, based on the delay selected table 71 - rx delay select register address (hex): 0x0299 (1 reg) direct access defines the exter nal sram configuration. reset value (hex): 0000 bit # type description table 69 - sram control register (continued)
mt90222/3/4 data sheet 105 zarlink semiconductor inc. address (hex): 0x02ad (1 reg) direct access reset value (hex): 0000 bit # type description 15:0 r each bit reports the recombiner status fo r a link. a 1 means that the recombiner is enabled. the bit 15 reports for link 15, bit 14 reports for link 14 and so on so forth. do not write to this register. table 72 - enable recombiner status register address (hex): 0x0300 - 0x0307 (8 reg) direct access 1 register per tx ima group.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): b0 bit # type description 15:9 r unused. read all 0?s. 8 r/w reserved. write 0 for normal operation. 7:6 r/w value of m. these 2 bits spec ifies the value of m for the ima group. 00: m = 32 01: m = 64 10: m = 128 11: m = 256 5 r/w timing mode inserted in icp cell. a 0 means that the itc timing mode is inserted in the icp cell and a 1 means that the ctc timing mode is inserted in the icp cell. 4 r/w timing mode in roundrobin scheduler. a 0 means that the itc timing mode is selected and a 1 means that the ctc timing mode is selected for internal operation. 3:0 r/w reference link. these 4 bits define which physical link is to be used as reference for timing purposes. table 73 - tx group control mode registers address (hex): 0x0310 - 0x0317 (8 reg) direct access 1 register per 2 links, used in ima mode only. link 0 is paired with link 8, link 1 with link 9, and so on. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): physical link # bit # type description 15:8 r/w defines the icp cell offset of link n+8. the value of m de termines which significant bits are used as follows: m = 256; bits 7-0 are used, m = 128; bits 6-0 are used, m = 64; bits 5-0 are used, m = 32; bits 4-0 are used. table 74 - tx icp cell offset registers
mt90222/3/4 data sheet 106 zarlink semiconductor inc. 7:0 r/w defines the icp cell offset of link n. the value of m determines which significant bits are used as follows: m = 256; bits 7-0 are used, m = 128; bits 6-0 are used, m = 64; bits 5-0 are used, m = 32; bits 4-0 are used. address (hex): 0x0318 - 0x031f (8 reg) direct access 1 register pe r 2 links, link 0 is paired with link 8, link1 with link 9 and so on. the msbyte contains control the link 8-9 and lsbyte control links 0-7 reset value (hex): 0808 bit # type description 15 r/w write 1 to count all user cells sent on the tx tdm link n+8. write 0 to count the total number of cell sent on the tx tdm link n+8. 14 r/w set to 1 to start sending user cells in ima mode on link n+8. set to 0 to send always filler and icp cells in ima mode (note: in non-ima mode, the control to send user cells is implemented with the utopia input link phy enable register). 13 r/w coset value. a 0 will generate hec with coset value. when 1, coset is not added. 12 r/w cell scrambling. a 1 enables the scrambling of the cells on the link n+8. 11 r/w set to 1 for non-ima mode and clear to 0 for ima mode. select the ima group number before enabling the ima mode. 10:8 r/w defines ima group number when the link is configured in ima mode. select the ima group number before enabling the ima mode. when configuring the link in non-ima mode after it was in ima mode, do not change the ima group number until the link is reported in non-ima mode (refer to tx im a mode status register). 7 r/w write 1 to count all user cells sent on the tx tdm link n. write 0 to count the total number of cells sent on the tx tdm link n. 6 r/w set to 1 to start sending user cells in ima mode. set to 0 to send continuously filler and icp cells in ima mode (note: in non-ima mode, the control to send user cells is implemented with the utopia input link phy enable register). 5 r/w coset value. a 0 will generate hec with coset value, when 1, coset is not added. 4 r/w cell scrambling. a 1 enables the scrambling of the cells on the link n. 3 r/w set to 1 for non-ima mode and clear to 0 fo r ima mode. select the ima group number before enabling the ima mode. table 75 - tx link control registers address (hex): 0x0310 - 0x0317 (8 reg) direct access 1 register per 2 links, used in ima mode only. link 0 is paired with link 8, link 1 with link 9, and so on. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): physical link # bit # type description table 74 - tx icp cell offset registers (continued)
mt90222/3/4 data sheet 107 zarlink semiconductor inc. 2:0 r/w defines ima group number when the link is configured in ima mode. select the ima group number before enabling the ima mode. when configuring the link in non-ima mode after it was in ima mode, do not change the ima group number until the link is reported in non-ima mode (refer to tx im a mode status register). address (hex): 0x0321 - 0x0324 (4 reg) direct access 1 register per 2 ima group ima. gr oup 0 is paired with ima group 4, ima group 1 with ima group 5 and so on.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 3030 bit # type description 15 r/w 0 for stuff indication 1 frame before stuff event for ima group n+4. 1 for stuff indication 4 frames before stuff event. 14:11 r/w overflow limit for ima group n+4. default is 6. 10:8 r/w underflow limit for im a group n+4. default is 1. 7 r/w 0 for stuff indication 1 frame before stuff event for ima group n. 1 for stuff indication 4 frames before stuff event. 6:3 r/w level overflow limit. default is 6 for ima group n. 2:0 r/w level underflow limit. de fault is 1 for ima group n. table 76 - tx ima control registers address (hex): 0x0333 (1 wr ite only/read only register) direct access the read value is independent from the written value.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:0 r reserved 15:10 w unused 9:4 w reserved. write "010000" respectively to bit 9:4 3 w write 1 with ima group number in bits 2: 0 when adding a link to an existing ima group. write 0 when the link is reported in ima mode. 2:0 r/w write ima group number to which a link is added. table 77 - tx add link control register address (hex): 0x0318 - 0x031f (8 reg) direct access 1 register pe r 2 links, link 0 is paired with link 8, link1 with link 9 and so on. the msbyte contains control the link 8-9 and lsbyte control links 0-7 reset value (hex): 0808 bit # type description table 75 - tx link control registers (continued)
mt90222/3/4 data sheet 108 zarlink semiconductor inc. address (hex): 0x0336 - 0x033d (8 reg) direct access 1 register per 2 links, used in ima mode only. link 0 is paired with link 8, link 1 is paired with link 9 and so on. reset value (hex): physical link # bit # type description 15:13 r/w reserved. write all 0?s. 12:8 r/w link id for the link n+8. the value can be between 0 and 31. this is the logical value associated to a physical link. used in ima mode only. 7:5 r/w reserved. write all 0?s. 4:0 r/w link id for the link n. the value can be between 0 and 31. this is the logical value associated to a physical link. used in ima mode only. table 78 - tx link id registers address (hex): 0x0345 (1 reg) direct access 1 register for all links. reset value (hex): 0000 bit # type description 15:0 r a 1 indicates a specific link (1 link pe r bit 15:0) is in ima mode and started by the roundrobin scheduler. table 79 - tx link active status register address (hex): 0x0346 (1 reg) direct access 1 register for all links. reset value (hex): ffff bit # type description 15 r 1 means link 15 is not in ima mode. 14 r 1 means link 14 is not in ima mode. ... ... ... 1 r 1 means link 1 is not in ima mode. 0 r 1 means link 0 is not in ima mode. table 80 - tx ima mode status register
mt90222/3/4 data sheet 109 zarlink semiconductor inc. address (hex): 0x0401 (1 reg) direct access 1 register for all groups.for mt90222 only groups 0,1,2 and 3 are used. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7 r/w 0: count total cells for group 7. 1: count only user cells for group 7. 6 r/w 0: count total cells for group 6. 1: count only user cells for group 6. ... ... ... 1 r/w 0: count total cells for group 1. 1: count only user cells for group1. 0 r/w 0: count total cells for group 0. 1: count only user cells for group 0. table 81 - utopia input cell counter groups register address (hex): 0x0402 (1 reg) direct access 1 register for all links. reset value (hex): 0000 bit # type description 15 r/w 0: count total cells for link 15. 1: count only user cells for link 15. 14 r/w 0: count total cells for link 14. 1: count only user cells for link 14. ... ... ... 1 r/w 0: count total cells for link 1. 1: count only user cells for link 1. 0 r/w 0: count total cells for link 0. 1: count only user cells for link 0. table 82 - utopia input cell counter links register address (hex): 0x0403 - 0x0406 (4 regs) direct access 1 register per 2 tx ima groups. ima group n is paired with ima group n+4.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0c0c bit # type description 15:12 r unused. read all 0?s. table 83 - tx idcr integration registers
mt90222/3/4 data sheet 110 zarlink semiconductor inc. 11:8 r/w defines the integrat ion period for ima group n+4: 1111: reserved, do not use 1110: 2 22 clock cycles ..... 0001: 2 09 clock cycles 0000: 2 08 clock cycles 7:4 r/w reserved. 3:0 r/w defines the integration period for ima group n: 1111: reserved, do not use 1110: 2 22 clock cycles 1101: 2 21 clock cycles 1100: 2 20 clock cycles (preferred value for e1) 1011: 2 19 clock cycles (preferred value for t1 - 24 channels) 1010: 2 18 clock cycles 1001: 2 17 clock cycles (preferred value for t1 - 23 channels) 1000: 2 16 clock cycles 0111: 2 15 clock cycles 0110: 2 14 clock cycles 0101: 2 13 clock cycles 0100: 2 12 clock cycles 0011: 2 11 clock cycles 0010: 2 10 clock cycles 0001: 2 09 clock cycles 0000: 2 08 clock cycles address (hex): 0x040b (1 reg) direct access 1 register for all 8 status bits. reset value (hex): 0000 bit # type description 15:8 r unused. read 0?s. 7:0 r/w each bit set to ?1? will en able the generation of the interrupt when the corresponding bit in the irq ima group overflow status register is set. there is one bit for each status bit. table 84 - irq ima group overflow enable register address (hex): 0x0403 - 0x0406 (4 regs) direct access 1 register per 2 tx ima groups. ima group n is paired with ima group n+4.for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0c0c bit # type description table 83 - tx idcr integration registers (continued)
mt90222/3/4 data sheet 111 zarlink semiconductor inc. address (hex): 0x040c (1 reg) direct access 1 register to enable interrupts from ima groups. the rxclk signal must be active for correct register operation. fo r mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r/w when set to 1, the corresponding bit in the overflow status r egister can generate an interrupt. a value of 0 inhibits the gener ation of an interrupt. ima groups 7:0. table 85 - rx utopia ima group fifo overflow irq enable register address (hex): 0x040e (1 reg) direct access reset value (hex): 0000 bit # type description 15:4 r unused. read all 0?s 3 r/w set when the utopia output clock is missing or too slow. this latched bit is cleared by writing a 0. 2 r/w set when the utopia input clock is missing or too slow. this latched bit is cleared by writing a 0. 1 r/w overflow of 1 or more of the tx utopia fifo. 0 r/w set when there is no free cell in tx cell ra m. this latched bit is cleared by writing a 0. table 86 - general status register address (hex): 0x040f (1 reg) synchronized access reset value (hex): 0080 bit # type description 15:12 r/w unused. read all 0?s. 11 r/w reserved. write 0 for normal operation. 10 r/w counter values are latched when this bit is changed from 0 to 1 and bit 9:8 are set to 11. writing 0 has no effect. 9:8 r/w write 00 for normal operatio n without using the latch made. write 01 to latch the counter value at ever y rising edge of the signal at latchclk pin. write 10 to latch the counter value every 8 000 rising edges of the signal at latchclk pin. write 11 to latch the counter value every time bit 10 of this regist er is written to 1. 7 r/w write: 0 for normal operation. read: 1 when the transfer is done, 0 when the transfer is pending. 6 r/w toggle bit. toggles with every write acce ss to mt90222/3/4.write 0 for normal operation. 5 r/w reserved. write 0 for normal oper ation. read value is undetermined. 4 r/w reserved. write 0 for normal operation. table 87 - counter transfer command register
mt90222/3/4 data sheet 112 zarlink semiconductor inc. 3 r/w value to write to the enable bit. 1 to enable, 0 to mask interrupt. this value is transferred when the bit 1:0 are 10. 2 r/w 0 will enable the transfer from the up to the selected counter. 1 will enable the transfer from the selected counter to the up. 1:0 r/w 00: initialize al l the counters with 0. 01: initiate a read or wr ite of the counter value. 10: initiate a read or write of the irq enable counter bit. 11: unused. address (hex): 0x0410 - 0x041f (16 reg) direct access 1 register per link. the rxclk and txclk signals must be active for correct register operation. reset value (hex): 0000 bit # type description 15:13 r unused. read all 0?s. 12 r/w this bit is set when the rx utopia fi fo associated with a link in non-ima mode overflows. this bit is cleared by writing 0. 11 r/w this bit is set when the utopia input counter for all cells (or all stuff cells event) associated with a link used in non-ima mode ov erflows. this bit is cleared by writing 0. 10 r/w this bit is set when the utopia input counter for idle cells associated with a link used in non-ima mode overflows. this bit is cleared by writing 0. 9 r/w this bit is set when the utopia input counter for unassigned cells associated with a link used in non-ima mode overflows. this bit is cleared by writing 0. 8 r/w this bit is set when the utopia input counte r for hec errored cells associated with a link used in non-ima mode overflows. th is bit is cleared by writing 0. 7 r/w this bit is set when the tx tdm link counter for all cells associated with a link overflows. 6 r/w this bit is set when the tx tdm link counter for idle or filler cells associated with a link overflows. 5 r/w this bit is set when the tx tdm link counter for tx stuff cells associated with a link overflows. 4 r/w this bit is set when the tx tdm link counter for tx icp cells associated with a link overflows. 3 r/w this bit is set when the rx tdm link counter for all cells (or all stuff cells event) associated with a link overflows. 2 r/w this bit is set when the rx tdm link counter for idle or filler cell s associated with a link overflows. 1 r/w this bit is set when the rx tdm link counter for hec errored cells associated with a link overflows. table 88 - irq link tc overflow status registers address (hex): 0x040f (1 reg) synchronized access reset value (hex): 0080 bit # type description table 87 - counter transfer command register (continued)
mt90222/3/4 data sheet 113 zarlink semiconductor inc. 0 r/w this bit is set when the rx tdm link counter for bad icp cells associated with a link overflows. address (hex): 0x0420 - 0x0427 (8 reg) direct access 1 register per ima group. the rxclk and txclk signals must be active for correct register operation. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): 0000 bit # type description 15:5 r unused. read 0?s. 4 r/w this bit is set when the rx utopia fifo associated with an ima group overflows. this bit is cleared by writing 0. 3 r/w this bit is set when the counter for all cells associated with an ima group overflows. (input utopia port). this bit is cleared by writing 0. 2 r/w this bit is set when the counter for idle cells associated with an ima group overflows. (input utopia port). this bit is cleared by writing 0. 1 r/w this bit is set when the counter for unassigned cells associated with an ima group overflows. (input utopia port). this bit is cleared by writing 0. 0 r/w this bit is set when the counter for hec errored cells associated with an ima group overflows. (input utopia port). this bit is cleared by writing 0. table 89 - irq ima overflow status registers address (hex): 0x0430 (1 reg) synchronized access the value in this register is used for internal access to the counter when the transfer command is issued. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r/w a read accesses the msb (byte #3) of the counter selected in the select counter register. a write will hold the value to be written to the selected counter. table 90 - counter upper byte address (hex): 0x0410 - 0x041f (16 reg) direct access 1 register per link. the rxclk and txclk signals must be active for correct register operation. reset value (hex): 0000 bit # type description table 88 - irq link tc overflow status registers (continued)
mt90222/3/4 data sheet 114 zarlink semiconductor inc. address (hex): 0x0431 (1 reg) synchronized access the value in this register is used for internal access to the counter when the transfer command is issued. reset value (hex): 0000 bit # type description 15:0 r/w a read accesses the byte #2 and byte #1 of the counter that was selected in the select counter register. byte 2 is in bi ts 15:8 and byte 1 is in bits 7:0. a write will hold the value to be written to the selected counter. table 91 - counter bytes 2 and 1 register address (hex): 0x0432 (1 reg) synchronized access the value in this register is used for internal access to the counter when the transfer command is issued. reset value (hex): 0000 bit # type description 15:9 r unused. read all 0?s. 8:5 r/w the valid bit combinations are: 1011: utopia input, counter of all cells for link 1010: utopia input, counter of idle cells for link 1001: utopia input, counter of unassigned cells for link 1000: utopia input, counter of cells with hec error, single or multiple bit errors 0111: tx link, total number of cells, (or user cells) 0110: tx link, number of idle/filler cells 0101: tx link, number of stuff cells 0100: tx link, number of icp cells 0011: rx link, total number of cells (or stuff cells) 0010: rx link, number of idle /filler cells, (or user cells) 0001: rx link, number of cells with hec errors 0000: rx link, number of bad icp cells other values are not valid and should not be used. 4:0 r/w the valid bit combinations are: 10111: ima group 7 when utopia input counter access 10010: ima group 6 when utopia input counter access ... 10001: ima group 1 when utopia input counter access 10000: ima group 0 when utopia input counter access 01111: link 15 01110: link 14 ... 00000: link 0 other values are not valid and should not be used. table 92 - select counter register
mt90222/3/4 data sheet 115 zarlink semiconductor inc. address (hex): 0x0433 (1 reg) direct access 1 register for all 16 links. reset value (hex): 0000 bit # type description 15:0 r/w each bit represents a link. a ?1? means that the interrupt form the corresponding link is enabled and that the level of the irq pin is lo w if the corresponding bit in the irq master register is set. a?0? means that the irq level is not affected by the corresponding bit. table 93 - irq master enable register address (hex): 0x0434 (1 reg) direct access 1 register to enable interrupts fr om the links in tc mode. the rxclk signal must be active for correct register operation. reset value (hex): 00 bit # type description 15:0 r/w when set to 1, any bit set in the irq link tc overflow status register can generate an interrupt. a value of 0 inhibits the generati on of an interrupt. each bit corresponds to 1 link. table 94 - irq link tc overflow enable register address (hex): 0x0435 - 0x0444 (16 reg) direct access 1 status register per link. reset value (hex): 0000 bit # type description 15:12 r unused. read all 0?s. 11 r/w a ?1? indicates the end of the lo ds condition. cleared by writing a ?0?. 10 r/w a ?1? indicates the end of the lif condition. cleared by writing a ?0?. 9 r/w a ?1? indicates the end of the l cd condition. cleared by writing a ?0?. 8 1 r a ?1? in this bit means that at least one of the irq sources from the ima group overflow status register is requesting service. this bi t can be cleared only by servicing the source of the irq. this bit is valid only for the irq link 0 status register and is read ing always a 0 for the irq link 1-15 st atus registers. 7 2 r/w a 1 in this bit means that at least one of th e ready bit used to initiate a transfer of a tx icp cell for at least 1 of the ima group is returned to 1 (meaning that the transfer of the tx icp cell is complete) or a frame pulse was detected for an ima group. this bit is cleared by writing a 0 to it. this bit is valid only for the irq link 0 status register and is read ing always a 0 for the irq link 1-7 status registers. 6 r/w overflow in the icp pre-processing ram. th is status bit can be cleared by writing a ?0? to it. 5 r/w icp cell with changes received. the link has received an icp cell which contain one or more changes in it. this status bit ca n be cleared by writing a ?0? to it. table 95 - irq link status registers
mt90222/3/4 data sheet 116 zarlink semiconductor inc. 4 r/w iv. the link has received an icp cell which contain a violation as defined in table 16 of ima spec. this status bit can be cleared by writing a ?0? to it. 3 r/w lods. the link is out of delay synchronizati on. this status bit can be cleared by writing a ?0? to it. 2 r/w lif. loss of ima frame. this status bit can be cleared by writing a ?0? to it. 1 r/w lcd loss of cell delineation. this status bit can be cleared by writing a ?0? to it. 0 r link counter overflow interrupt. one or more counters associated with the link overflowed. this status bit can be cleared only by reading or writing to the counter(s) which is (are) the source for the irq. 1. bit is present only for link 0. in all other link status registers, this bit is set to 0. 2. bit is present only for link 0. in all other link status registers, this bit is set to 0. address (hex): 0x0445 - 0x0454 (16 reg) direct access 1 enable register per link status reg. reset value (hex): 0000 bit # type description 15:12 r unused. read all 0?s. 11:0 r/w each bit set to ?1? will enable the generation of the interrupt when the corresponding bit in the irq link status register is set. table 96 - irq link enable registers address (hex): 0x0455 (1 reg) direct access 1 register for all 16 links. reset value (hex): 0000 bit # type description 15:0 r each bit represents a link. a ?1? means that the corresponding link has a valid request for interrupt. the level of the irq pin is controlled by the bits in this register and the corresponding bits in the irq master enable register. a write does not have any affect on the bits in this register. the status bit is not latched and changing the mask bit in the irq master register has a direct ef fect on the level of the irq pin. table 97 - irq master status register address (hex): 0x0435 - 0x0444 (16 reg) direct access 1 status register per link. reset value (hex): 0000 bit # type description table 95 - irq link status registers (continued)
mt90222/3/4 data sheet 117 zarlink semiconductor inc. address (hex): 0x0457 (1 reg) direct access 1 register for all ima groups. reset value (hex): 0000 bit # type description 15:8 r unused. read all 0?s. 7:0 r/w each bit set to ?1? represent an overflow condition from the ima group associated with the bit. there is one bit for each ima group. a bi t is set when one or more of the 4 counters or the rx utopia fifo associated with an ima group overflows. table 98 - irq ima group overflow status register address (hex): 8 blocks of 32 words (16 bits) from 0x0500 to 0x05ff direct access access these locations directly then use transfer command to copy to internal memory. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): these registers need to be initialized for proper operation. address offset (hex) type atm byte # msb, lsb description 00 r/w 2, 1 lsb: byte 1 (header 1 byte) of icp cell. the value should be set to 0x00 msb: byte 2 (header 2 byte) of icp cell. the value should be set to 0x00 01 r/w 4, 3 lsb: byte 3 (header 3 byte) of icp cell. the value should be set to 0x00 msb: byte 4 (header 4 byte) of icp cell. the value should be set to 0x0b 02 r/w 6, 5 lsb: hec is always calculated and inserted by the mt90222/3/4. msb: oam, should be set to either 0x01 or 0x03 03 r/w 8, 7 lsb: cell id, link id. the bit 7 (cell id) is controlled by the mt90222/3/4, the link id is provided by the tx link id register. msb: ima frame sequence number. inserted by the mt 90222/3/4. 04 r/w 10, 9 lsb: icp cell offset. inserted by the mt90222/3/4 based on the link offset register info. msb: link stuff indication. inserted by the mt90222/3/4 05 r/w 12, 11 lsb: status & control ch ange indication. inserted by the mt9 0222/3/4. msb: ima id 06 r/w 14, 13 lsb: group status and control msb: synchronization information, inserted by the mt90222/3/4 07 r/w 16, 15 lsb: tx test control msb: tx test pattern 08 r/w 18, 17 lsb: rx test pattern msb: status and control of links with lid = 0 09- 17 r/w 48, 19 status and control of links wi th lid in the range 1-30 (odd numbered byte in lsb and even numbered byte in msb) 18 r/w 50, 49 lsb: status and control of links with lid = 31 msb: unused, should be set to 0x6a 19 r/w 51, 52 lsb: end-to-end channel msb: upper 2 bits of the crc-10. inserted by the mt9 0222/3/4 table 99 - tx ima icp cell registers
mt90222/3/4 data sheet 118 zarlink semiconductor inc. 1a r/w ---, 53 lsb: lower 8 bits of the crc-10. inserted by the mt90 222/3/4 msb: not used by mt90222/3/4. 1b-1f r/w --- --- lsb: not used by mt90222/3/4. msb: not used by mt90222/3/4. address (hex): 0x0600 - 0x060f (16 reg) direct access 1 reg. per tx link. reset value (hex): 0000 bit # type description 15 r unused. read 0. 14:10 r/w clock source select these 4 bits are used to select the source for the txck for the link when txck and tx sync are defined as outputs: the valid combinations are: 00000: rxck0 00001: rxck1 00010: rxck2 00011: rxck3 00100: rxck4 00101: rxck5 00110: rxck6 00111: rxck7 01000: rxck8 01001: rxck9 01010: rxck10 01011: rxck11 01100: rxck12 01101: rxck13 01110: rxck14 01111: rxck15 10000: refck0 10001: refck1 10010: refck2 10011: refck3 9 r/w clock and sync direction when 0, txck and txsync are outputs. when 1, txck and txsync are inputs. 8 r/w remote loopback when 1, txck, txsync and dsto come from the rx pins of the same link. when 0. normal mode. 7 r/w link enable when 0, the tx port is in high impedance mode when 1, the tx port is active 6:5 r/w data rate: 11: 8.192 mb/sec. 10: 4.096 mb/sec. 01: 2.048 mb/sec 00: 1.544 mb/sec table 100 - tdm tx link control register address (hex): 8 blocks of 32 words (16 bits) from 0x0500 to 0x05ff direct access access these locations directly then use transfer command to copy to internal memory. for mt90222 only groups 0, 1, 2 and 3 are used. reset value (hex): these registers need to be initialized for proper operation. address offset (hex) type atm byte # msb, lsb description table 99 - tx ima icp cell registers (continued)
mt90222/3/4 data sheet 119 zarlink semiconductor inc. 4:3 r/w multiplex mode select: 00: no multiplexing, 01: multiplex on a per byte basis, 2 links to 1 link. valid only for st-bus mode when txck and txsync are inputs. 10: multiplex on a per byte basis, 4 links to 1 link. valid only for st-bus mode when txck and txsync are inputs. 2 r/w clock and sync format: when 0, tdm is in generic mode: clock is 1x data rate and sync is 1 bit long at beginning of frame. when 1, tdm is st-bus format: clock 2x data rate and sync as per st-bus format 1 r/w clock polarity: when 0, the data is output/sampl ed at the falling edge of txck when 1, the data is output/sampled at the rising edge of txck this bit is ignored in st-bus format. 0 r/w sync polarity: when 0, the sync pulse is active low when 1, the sync pulse is active high. this bit is ignored in st-bus format. address (hex): 0x0610 - 0x061f (16 reg) direct access control time slot 15:0. reset value (hex): 0000 bit # type description 15:0 r/w each bit controls if the corresponding time slot is used to carry atm traffic. when not in use, the dsto pin is in high z mode for the corresponding time slot. this registers controls time slots 15:0. table 101 - tdm tx mapping (timeslots 15:0) register address (hex): 0x0620 - 0x062f (16 reg) direct access control time slot 31:16 reset value (hex): 0000 bit # type description 15:0 r/w each bit controls if the corresponding time slot is used to carry atm traffic. when not in use, the dsto pin is in high z mode for the corresponding time slot. this registers controls time slots 31:16. fo r t1 links, bit 8 (timeslot 24) must be zero. table 102 - tdm tx mapping (timeslots 31:16) register address (hex): 0x0600 - 0x060f (16 reg) direct access 1 reg. per tx link. reset value (hex): 0000 bit # type description table 100 - tdm tx link control register (continued)
mt90222/3/4 data sheet 120 zarlink semiconductor inc. address (hex): 0x0630 (1 reg) direct access 1 reg. for all 16 txck signals. reset value (hex): 0000 bit # type description 15 r when 1: txck faulty on link 15. 14 r when 1: txck faulty on link 14. ... r .... 1 r when 1: txck faulty on link 1. 0 r when 1: txck faulty on link 0. table 103 - txck status register address (hex): 0x0631 (1 reg) direct access 1 reg. for all 16 rxck signals. reset value (hex): 0000 bit # type description 15 r when 1: rxck faulty on link 15. 14 r when 1: rxck faulty on link 14. ... r .... 1 r when 1: rxck faulty on link 1. 0 r when 1: rxck faulty on link 0. table 104 - rxck status register address (hex): 0x0632 (1 reg) direct access 1 reg. for all 4 refck signals. reset value (hex): 0000 bit # type description 15:4 r unused. read 0?s 3 r when 1: refck3 faulty 2 r when 1: refck2 faulty 1 r when 1: refck1 faulty 0 r when 1: refck0 faulty table 105 - refck status register
mt90222/3/4 data sheet 121 zarlink semiconductor inc. address (hex): 0x0633 (1 reg) direct access 1 reg. for all 16 rx links. reset value (hex): 0000 bit # type description 15 r/w txsync sync signal faulty on link 15. cleared by writing ?0?. 14 r/w txsync sync signal faulty on link 14. cleared by writing ?0?. ... r/w .... 1 r/w txsync sync signal faulty on link 1. cleared by writing ?0?. 0 r/w txsync sync signal faulty on link 0. cleared by writing ?0?. table 106 - tx sync. status register address (hex): 0x0634- 0x0635 (2 reg) direct access reset value (hex): 0000 bit # type description 15:5 r unused. read all 0?s. 4:0 r/w these 5 bits are used to select the source for the signal at pllref0: the valid combinations are: 00000: rxck0 01000: rxck8 10000: rxsync0 11000: rxsync8 00001: rxck1 01001: rxck9 10001: rxsync1 11001: rxsync9 00010: rxck2 01010: rxck10 10010: rxsync2 11010: rxsync10 00011: rxck3 01011: rxck11 10011: rxsync3 11011: rxsync11 00100: rxck4 01100: rxck12 10100: rxsync4 11100: rxsync12 00101: rxck5 01101: rxck13 10101: rxsync5 11101: rxsync13 00110: rxck6 01110: rxck14 10110: rxsync6 11110: rxsync14 00111: rxck7 01111: rxck15 10111: rxsync7 11111: r xsync15 table 107 - pll reference control register address (hex): 0x0700 - 0x070f (16 reg) direct access 1 reg. per rx link. reset value (hex): 0000 bit # type description 15:12 r unused. read 0?s. 11 w reserved. write 0 for normal operation. 10 r/w automatic atm cell synchronization when 1: automatic atm cell synchroniza tion enabled. to be used when no rxsync signal is provided. register 0x0741 must also be initialized. when 0: automatic atm cell synchronization disabled. 9 r/w reserved. write 0 for normal operation. table 108 - tdm rx link control register
mt90222/3/4 data sheet 122 zarlink semiconductor inc. 8 r/w digital loopback mode when 1, loopback mode, rxck, rxsync and dsti come from the tx pins of the same link. both tx and rx blocks operate normally. when 0, normal mode, rxck, rxsync and dsti come from the rx pins of the link 7 r/w link enable: 0: rx port is not active 1: rx port is active 6:5 r/w data rate: 11: 8.192 mb/sec. 10: 4.096 mb/sec. 01: 2.048 mb/sec 00: 1.544 mb/sec 4:3 r/w multiplex mode select: 00: no demultiplexing, 01: demultiplex on a per byte basis, 1 link to 2 links. valid only for st-bus mode when txck and txsync are inputs. 10: demultiplex on a per byte basi s, 1 link to 4 links. valid only for st-bus mode when txck and txsync are inputs. 2 r/w clock and sync format: when 0, tdm is in generic mode: clock is 1x data rate and sync is 1 bit long at beginning of frame. when 1, tdm is st-bus format: clock 2x data rate and sync as per st-bus format 1 r/w clock polarity: when 0, the data is sampled at the rising edge of rxck when 1, the data is sampled at the falling edge of rxck this bit is ignored in st-bus format. 0 r/w sync polarity: when 0, the sync pulse is active low when 1, the sync pulse is active high. this bit is ignored in st-bus format. address (hex): 0x0710 - 0x071f (16 reg) direct access control time slot 15:0. reset value (hex): 0000 bit # type description 15:0 r/w each bit controls if the corresponding time slot is used to carry atm traffic. when not in use, the dsti pin is ignored for the corresponding time slot this registers controls time slots 15:0. table 109 - tdm rx mapping (timeslots 15:0) register address (hex): 0x0700 - 0x070f (16 reg) direct access 1 reg. per rx link. reset value (hex): 0000 bit # type description table 108 - tdm rx link control register (continued)
mt90222/3/4 data sheet 123 zarlink semiconductor inc. address (hex): 0x0720 - 0x072f (16 reg) direct access control time slot 31:16. reset value (hex): 0000 bit # type description 15:0 r/w each bit controls if the corresponding time slot is used to carry atm traffic. when not in use, the dsti pin is ignored for the corresponding time slot this registers controls time slots 31:16. fo r t1 links, bit 8 (timeslot 24) must be zero. table 110 - tdm rx mapping (timeslots 31:16) register address (hex): 0x0730 (1 reg) direct access 1 reg. for all 16 rx links. reset value (hex): 0000 bit # type description 15 r/w rxsync signal faulty on link 15. cleared by writing ?0?. 14 r/w rxsync signal faulty on link 14. cleared by writing ?0?. ... r/w .... 1 r/w rxsync signal faulty on link 1. cleared by writing ?0?. 0 r/w rxsync signal faulty on link 0. cleared by writing ?0?. table 111 - rx sync. status register address (hex): 0x0741 (1 reg) direct access 1 reg. for all rx links. reset value (hex): 0000 bit # type description 15:8 r unused. read 0?s. 7:0 r/w must write with 54 (0x36) in bit mode cell delineation. not used in byte mode cell delineation. table 112 - rx automatic atm synchronization register address (hex): 0x0800 - 0x0bff, 32 blo cks of 32 words (16 bit wide) direct access access these locations directly, then use the transfer command to copy to internal memory. reset value (hex): unknown address offset (hex) type description 00 r/w old icp cell, link 0. 20 r/w new icp cell, link 0. 40 r/w old icp cell, link 1. table 113 - rx ima icp cell
mt90222/3/4 data sheet 124 zarlink semiconductor inc. 8.0 application notes inverse multiplexing for atm (ima) divides a high-bandwidth stream of atm cells in a round-robin fashion and sends them over grouped t1/e1/j1 or dsl lines in a logical connec tion (on public or private networks) and recombines the cells to recover the original high-band width stream at the receiving end. za rlink?s mt90222/3/4 is ideally suited to implement the ima function. 8.1 connecting the mt90222/ 3/4 to various t1/e1/j1 framers many off-the-shelf t1/e1/j1 framers r equire the generation of a 1.544 mhz or 2.048 mhz transmit clock reference signal at an input pin. the mt9042 ca n generate both of these clocks and th e st-bus back-plane signals (c4,f0). figure 20 provides an example implementation using existing t1/e1/j1 framers and a common 2 mbps st-bus backplane. new generation zarlink framers only require the st-bus 4.096 mhz (c4) clock and a frame pulse (f0i) at the transmit interface. an internal pll generates the re quired 1.544 mhz or 2.048 mh z transmit clock. figure 21 provides an example of an ima implementation based on the zarlink mt90224 and the zarlink mt9076 framers. this configuration supports ctc mode. althoug h the mt9076 use the st-bus format, it is not configured as a common backplane. figure 22 exemplifies an ima implementation supporting the asynchronous link operation mode. each t1,e1/j1 framer uses independent clock and synchronizat ion signals which corresponds to itc mode. figure 23 exemplifies an ima implementation supporting the asynchronous link operation mode. each t1,e1/j1 framer uses independent clock and synchronization signals. figure 24 exemplifies an ima implementation supporting the asynchronous link operation mode where the txclk signal is provided by the t1 interface. each t1 fr amer uses independent clock and synchronization signals. 60 r/w new icp cell, link 1 ... ... ... 3a0 r/w new icp cell, link 14 3c0 r/w old icp cell, link 15 3e0 r/w new icp cell, link 15 address (hex): 0x0800 - 0x0bff, 32 blo cks of 32 words (16 bit wide) direct access access these locations directly, then use the transfer command to copy to internal memory. reset value (hex): unknown address offset (hex) type description table 113 - rx ima icp cell (continued)
mt90222/3/4 data sheet 125 zarlink semiconductor inc. figure 20 - synchronous st-bus mode (using st-bus/2.048 mbps backplane compatible framers) mt90224 device utopia bus st-bus i/fclocks atm layer bus tdm back-plane (st-bus) legacy trunks at 1.5 or 2 mbps legacy trunks at 1.5 or 2 mbps legacy trunks at 1.5 or 2 mbps mt9042 clock recovery and dejitter functions receive clock or 8 khz references (1.544 or 2.048 mhz) 8 khz 4.096 mhz dsto[0:15] dsti[0:15] txck[0-15] txsync[0-15] rxck[0-15] rxsync[0-15] st-bus i/f data data lines st-bus i/f data st-bus i/f data external source dejittered tx clk to framers (1.544 or 2.048 mhz) zarlink mt9076b framer/liu zarlink mt9076b framer/liu zarlink mt9076b framer/liu
mt90222/3/4 data sheet 126 zarlink semiconductor inc. figure 21 - ctc mode (using mt9076 b t1/e1/j1 single chip transceivers) mt90224 device utopia bus dsto c4b f0b dsti rxck[0] dsto[0] dsti[0] txck[0] txsync[0] mt9076b#1 dsto c4b f0b dsti rxck[15] rxsync[15] dsto[15] dsti[15] txck[15] txsync[15] mt9076b#n 20 mhz +/-50 ppm level 2 note: the mt9076 #1 is configured in line sync. mode and all other mt9076s are configured in bus sync mode. rxsync[0] txck[1:15] are sourced from rxck[0].
mt90222/3/4 data sheet 127 zarlink semiconductor inc. figure 22 - itc mode with st-bus (using zarlink mt9076b t1/e1/j1 single chip transceivers) mt90224 device utopia bus dsto c4b f0b dsti rxck[0] rxsync[0] dsto[0] dsti[0] txck[0] txsync[0] mt9076b dsto c4b f0b dsti rxck[15] rxsync[15] dsto[15] dsti[15] txck[15] txsync[15] mt9076b 20 mhz +/-50 ppm level 2 note: all mt9076b devices are configured in line sync. mode
mt90222/3/4 data sheet 128 zarlink semiconductor inc. figure 23 - itc mode with generic tdm inte rface (using mt9076b t1/e1/j1 framer/liu) mt9076b #1 mt90224 utopia bus atm layer bus legacy trunks at 1.5 or 2 mbps mt9042 transmit clock dejittering function dejittered tx clk legacy trunks at 1.5 or 2 mbps legacy trunks at 1.5 or 2 mbps 1.544 or 2.048 mhz dsto[15] dsti[15] txcki[15] txsynco[15] rxcki[15] rxsynci[15] tdm data (1.544 or 1.544 or 2.048 mhz 1.544 or 2.048 mhz 1.544 or 2.048 mhz dsto[0] dsti[0] txcki[0] txsynco[0] rxcki[0] rxsync[0] 8 khz [t7] 8 khz [t7] 8 khz [r7] 8 khz [r7] refck0-3 pllref0-1 external source tdm data 2.048 mhz) mt9076b in ima mode. mt9042 pll is optional. txck[i] is sourced from rxck[i] or refck[j] mt9076b #2 mt9076b #15 dsto dsti c4 fp exclk rxfp dsto dsti c4 fp exclk rxfp 1.544 or 2.048 mhz tdm data 1.544 or 2.048 mhz 8 khz [t7] 8 khz [r7] dsto dsti c4 fp exclk rxfp dsto[1] dsti[1] txcki[1] txsynco[1] rxcki[1] rxsync[1]
mt90222/3/4 data sheet 129 zarlink semiconductor inc. figure 24 - asynchronous operations (usi ng two mt9072 octal t1/e1/j1 framers) 8.2 connecting the mt90222/3/4 to shdsl framers traditionally, ima (inverse multiplexing for atm) is wi dely adopted in e1/ds1 applications. with the emergence of g.shdsl (single-pair high rate digital subscribe line) standards, it is now viable to apply ima over shdsl lines. this application note provides a solution of ima over up to 16 g.shdsl lines. it serves as a reference design of interfacing zl30228 to globespan virata?s orion chipset. mt90222/3/4 is the second-generation ima device from za rlink, which supports ima over 16 serial bit streams running at a maximum of 2.5 mbps. it also incorp orates a utopia level 2 bus as atm interface. the orion chipset contains a dual-channel dsl framer and two analog front-ends (afe). it offers a low-power high-density solution for g.shdsl applications. connecting mt90222/3/4 and orion chipset together provides us a complete solution for ima over g.shdsl that meets both ima specification and g.shdsl specification. the mt90224 ima device shown in this reference design can be replaced by MT90223 (octal) or mt90222 (quad), two ima devices from the same family. both MT90223 and mt90222 are pin and functional compatible to mt90224. a block-level diagram is represented in figure 25. mt90224 dsto[0] dsti[0] txckio[0] txsyncio[0] rxcki[0] rxsynci[0] tpos[0] dsti[0] fp[0] dsto[0] rxbf[0] rxdlc[0] tneg[0] rneg[0] rpos[0] dsto[15] dsti[15] txckio[15] txsyncio[15] rxcki[15] rxsynci[15] mt9072 #1 utopia bus level 2 note: the mt9072 is configured in ima mode. t2o[0] e2i[0] cki[0] tpos[7] tneg[7] rneg[7] rpos[7] t2o[70] e2i[7] dsti[7] fp[7] dsto[7] rxbf[7] rxdlc[7] cki[7] to liu to liu mt9072 #2
mt90222/3/4 data sheet 130 zarlink semiconductor inc. 8.2.1 modes of operation for mt90224, the following modes of operation must be selected and programmed: serial stream mode of up to 2.5 mb/s per link. txck is configured as input. recommended register settings: tdm tx link control register (0x600 ? 0x60f) should be set to 0x02a3. tdm tx mapping registers (0x610 ? 0x61f) should be set to 0xffff. tdm tx mapping registers (0x620 ? 0x62f) should be set to 0xffff. tdm rx link control register (0x700 ? 0x70f) should be set to 0x04a3. tdm rx mapping registers (0x710 ? 0x71f) should be set to 0xffff. tdm rx mapping registers (0x720 ? 0x72f) should be set to 0xffff. rx automatic synchronization regi ster (0x741) should be set to 0x0036 orion chipset provides both txclk and rxclk to mt90224. orion chipset should be configur ed in serial interface mode. zarlink?s msan - 208 application note describes the im a to g.shdsl connection in detail and also contains the reference design of the interface. for detailed programming of orion chipset, please refer to gl obespan?s application note an-073.
mt90222/3/4 data sheet 131 zarlink semiconductor inc. figure 25 - interface to shdsl device mt90224 link 6 link 12 link 0 orion dual channel microport interface link 3 link 1 link 13 link 5 orion dual channel link 14 orion dual channel link 4 orion dual channel orion dual channel link 7 link 10 orion dual channel link 15 orion dual channel link 2 link 11 orion dual channel link 8 link 9 utopia interface mt90224
mt90222/3/4 data sheet 132 zarlink semiconductor inc. 9.0 ac/dc characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note: input pins are 5 volt compatible type. ? typical figures are for design aid only. absolute maximum conditions* parameter symbol min. max. units 1 supply voltage (2.5 volt core) supply voltage (3.3 volt core) supply voltage (5.0 volt i/o) v 2.5 v 3.3 v dd5 -0.3 -0.3 -1.0 3.1 3.9 6.5 v 2 voltage at digital inputs (vdd5 connected to 3.3 v) voltage at digital inputs (vdd5 connected to 5.0 v) v i3.3 v i5.0 -1.0 -1.0 3.9 6.5 v 3 current at digital inputs i i -10 10 a 4 storage temperature t st -40 125 c recommended operating conditions - voltages are with respect to ground (vss) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 operating temperature t op -40 85 c 2 supply voltage v dd2.5 v dd3.3 v dd5.0 2.38 3.14 4.75 2.5 3.3 5.0 2.6 3.46 5.25 v dc electrical ch aracteristics* - voltages are with respect to ground (vss) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current i dd2.5 i dd3.3 310 25/ 29/ 38 425 50/ 90/ 156 ma system clock 52 mhz. tdm clock @ 2.5 mhz i dd3.3 typical for mt90222/3/4 respectively with atm traffic, no tdm ring. 2 input high voltage (digital inputs) v ih 2.0 5.5 v when vdd5 pins connected to 5.0 vdc 3 input low voltage (digital inputs) v il -0.5 0.8 v 4 input leakage i ilpd i il 35 -10 115 1 222 10 a for pins with pull-down resistors and v in = v ss for all remaining input pins and v in = v dd3.3 or v ss 5 input pin capacitance c i5v c i 4.6 4.0 pf 5v tolerant inputs all other inputs 6 output high voltage (digital outputs) v oh 2.4 v dd 3.3 v
mt90222/3/4 data sheet 133 zarlink semiconductor inc. * dc electrical characteristics are over recommended temperature and supply voltage. ? typical figures are at 25 c, v dd =3.3 v, and for design aid only: not guaranteed and not subject to production testing. 7 output high current (up_d[15:0], dsto[15:0], txsyncio[15:0], txclk[15:0]) i oh -6 ma source v oh =2.4 v 8 output high current utopia i oh -8 ma source v oh =2.4 v 9 output high current (all other digital outputs) -4 ma 10 output low voltage (digital outputs) v ol v ss 0.4 v 11 output low current (up_d[15:0], up_irq , dsto[15:0], txsyncio[15:0], txclk[15:0]) i ol 6masource v ol =0.4 v 12 output low current utopia i ol 8masource v ol =0.4 v 13 output low (all others) 4 14 output pin capacitance c o5v c o 4.6 4.0 pf for 5 v tolerant outputs for all other outputs 15 high impedance leakage (digital i/o) i oz -10 1 10 av oh = v ss or v dd 3.3 dc electrical character istics* (continued) - voltages are with respect to ground (vss) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions
mt90222/3/4 data sheet 134 zarlink semiconductor inc. note 1: greater than 50 mhz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52 mhz operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter. note 1: greater than 50 mhz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52 mhz operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter. note 2: urxpar is not valid fo r cases where urxclk low pulse is shorter than 7.9 nsec. ac electrical characteristics - utopia interface transmit timing ( 50 mhz) 1 - multi-phy operation with up to 4 input loads of 10 pf each (40 pf total). signal name dir item description min. max. utxclk a->p f1 txclk frequency nominal (8-bit utopia mode) 0 50 mhz f1 txclk frequency nominal (16-bit utopia mode) 0 33 mhz tt2 txclk duty cycle 40% 60% tt3 txclk peak-to-peak jitter - 5% tt4 txclk rise/fall time - 2 ns utxdata[15:0], utxsoc, utxpar, utxenb , utxaddr[4:0] a->p tt5 input setup to txclk 4 ns - tt6 input hold from txclk 1 ns - utxclav[0] a<-p tod output delay from txclk - 14 ns tt8 output hold from txclk 1 ns - tt9 signal going low impedance to txclk 4 ns - tt10 signal going high impedance to txclk 0 ns - tt11 signal going low impedance from txclk 1 ns - tt12 signal going high impedance from txclk 1 ns - ac electrical character istics - utopia interface receive timing ( 50 mhz) 1 - multi-phy operation with up to 4 input loads of 10 pf each (40 pf total). signal name dir item description min. max. urxclk a->p f1 rxclk frequency (nominal) 0 50 mhz tt2 rxclk duty cycle 40% 60% tt3 rxclk peak-to-peak jitter - 5% tt4 rxclk rise/fall time - 2 ns urxenb , urxaddr[4:0] a->p tt5 input setup to rxclk 4 ns - tt6 input hold from rxclk 1 ns - urxdata[15:0], urxsoc, urxclav[0], urxpar 2 a<-p tod output delay from rxclk - 14 ns tt8 output hold from rxclk 1 ns - tt9 signal going low impedance to rxclk 4 ns - tt10 signal going high impedance to rxclk 0 ns - tt11 signal going low impedance from rxclk 1 ns - tt12 signal going high impedance from rxclk 1 ns -
mt90222/3/4 data sheet 135 zarlink semiconductor inc. ac electrical character istics - utopia interface transmit timing ( 25 mhz) - multi-phy operation with up to 8 input loads of 10 pf each (80 pf total). signal name dir item description min. max. utxclk a->p f1 txclk frequency (nominal) 0 25 mhz tt2 txclk duty cycle 40% 60% tt3 txclk peak-to-peak jitter - 5% tt4 txclk rise/fall time - 4 ns utxdata[15:0], utxsoc, utxpar, utxenb , utxaddr[4:0] a->p tt5 input setup to txclk 10 ns - tt6 input hold from txclk 1 ns - utxclav[0] a<-p tod output delay from txclk - 27 ns tt8 output hold from txclk 1 ns - tt9 signal going low impedance to txclk 10 ns - tt10 signal going high impedance to txclk 0 ns - tt11 signal going low impedance from txclk 1 ns - tt12 signal going high impedance from txclk 1 ns - ac electrical characteristics - ut opia interface receive timing ( 25 mhz) - multi-phy operation with up to 8 input loads of 10 pf each (80 pf total). signal name dir item description min. max. urxclk a->p f1 rxclk frequency (nominal) 0 25 mhz tt2 rxclk duty cycle 40% 60% tt3 rxclk peak-to-peak jitter - 5% tt4 rxclk rise/fall time - 4 ns urxenb , urxaddr[4:0] a->p tt5 input setup to rxclk 10 ns - tt6 input hold from rxclk 1 ns - urxdata[15:0], urxsoc, urxclav[0], urxpar a<-p tod output delay from rxclk - 27 ns tt8 output hold from rxclk 1 ns - tt9 signal going low impedance to rxclk 10 ns - tt10 signal going high impedance to rxclk 0 ns - tt11 signal going low impedance from rxclk 1 ns - tt12 signal going high impedance from rxclk 1 ns -
mt90222/3/4 data sheet 136 zarlink semiconductor inc. figure 26 - setup and hold time definition figure 27 - tri-state timing figure 28 - output delay timing note1: the utopia specification ac characteristics are ba sed on the timing specificatio n for the receiver side of a signal. in the case where the mt90222/3/ 4 is driving a signal (sending side), t he input setup to the (next) clock can be derived using the worst case peri od of the actual clock used. t is would be equivalent to tt5 or tt7 for the device that receives the output from the mt90222/3/4. t is = t clk_min - t od clock signal tt5, tt7 tt6, tt8 input setup to clock input hold from clock clock signal valid signal going high impedance t t10 1 signal tt11 signal going low impedance from clock tt12 signal going high impedance from clock t t9 1 clock signal valid signal t od t is 1 t clk_min
mt90222/3/4 data sheet 137 zarlink semiconductor inc. . note ? : typical figures are at 25 c, v dd =3.3 v, and for design aid only: not guaranteed and not subject to production testing. note 1: t rc = t clk - t csrs - t rds . figure 29 - external memory interface timing - read cycle ac electrical characteristics - external memory interface timing - read access item description min. typ. ? max. mt90222/3/4 system clock period 19 ns 20 ns t rc read cycle time 10 ns 1 t avrs address setup time 0 ns 9.5 ns t avrh address hold time 0 ns t csrs chip select setup time 1 ns 7.5 ns t csrh chip select hold time 1 ns t wers write enable* setup time 0 ns 9.5 ns t werh write enable* hold time 0 ns t rds data setup time 1.5 ns 0 t rdh data hold time 1 ns t csrs t csrh t avrh t wers t werh t rdh t avrs system clock sr_a[18:0] sr_cs sr_we sr_d[7:0] address valid data valid t rds t clk t rc note: sram control register table
mt90222/3/4 data sheet 138 zarlink semiconductor inc. note ? : typical figures are at 25 c, v dd =3.3 v, and for design aid only: not guaranteed and not subject to production testing. note 1: t wc = t clk - t csws. figure 30 - external memory interface timing - write cycle ac electrical characteristi cs - external memory interface timing - write access item description min. typ. ? max. t clk mt90222/3/4 system clock period 19 ns 20 ns t wc write cycle time 12.5 ns 1 t avws address setup time 0 ns 9.5 ns t avwh address hold time 0 ns t csws chip select setup time 1 ns 7.5 ns t cswh chip select hold time 1 ns 7.5 ns t wews write enable* setup time 0 ns 9.5 ns t wewh write enable* hold time 0 ns t wds data setup time 19 ns t wdh data hold time 0 ns t csws t cswh t avwh t wews t wewh t wds t wdh t avws system clock sr_a[18:0] sr_cs sr_we sr_d[7:0] address valid data valid t clk t wc note: the sr_we signal stays low until a read cycle is to be performed. refer to sram control register to select the number of cycles.
mt90222/3/4 data sheet 139 zarlink semiconductor inc. 9.1 cpu interface timing the cpu interface of the mt90222/3/4 supports both the mo torola and intel timing modes. no mode select pin is required. with motorola devices, the motorola r/w -signal is connected to the up_r/w pin and the up_oe pin is tied to ground. there is no ds signal and the up_cs signal is taken to access the mt90222/3/4. when used with intel devices, the read-signal is connected to the up_oe pin and the write-signal is connected to the up_r/w pin. when performing a read operation, data is pl aced on the bus immediately after up_cs is low and up_r/w is high for the motorola timing mode and after the up_cs and up_oe signals are low for intel timing. when performing a write operation in motorola timing mode, the data is clocked into an mt90222/3/4 pre-load register on the rising edge of up_r/w or up_cs signals. in intel timing mode, the data is clocked into mt90222/3/4 pre-load register on the rising edge of the up_r/w or up_cs signals. right after that transition, the data is transferred to the mt90222/3/4?s in ternal register. writing data into this register can take up 2 system clock cycles. figure 31 - cpu interface motorola timing - read access ac electrical characteristics - cpu interface motorola timing - read cycle characteristics sym. min. typ. max. units test conditions 1 r/w set-up time to up_cs falling edge t ws 1ns 2 data valid after up_cs falling edge. t acc 35 ns 150 pf loads 3 up_ad or up_r/w hold time after up_cs rising edge t ah 4ns 4 data hold time after rising edge of up_cs t ch 2ns 5 up_d low impedance after falling edge of up_cs t li 2 20 ns 150 pf loads up_cs address valid up_ad[11:0] up_r/w data valid up_d[15:0] t acc t ch t ws up_oe t ah t li (low)
mt90222/3/4 data sheet 140 zarlink semiconductor inc. figure 32 - cpu interface intel timing - read access ac electrical characteristi cs - cpu interface intel timing - read cycle characteristics sym. min. typ. max. units test conditions 1 r/w set-up time to up_cs falling edge t ws 1ns 2 data valid after both up_oe and up_cs are low. t acc 35 ns 150 pf loads 3 up_ad or up_r/w hold time after up_oe rising edge t ah 4ns 4 data hold time after the first rising edge of up_cs or up_oe t ch 2ns 5 up_d low impedance after falling edge of up_oe t li 2 20 ns 150 pf loads up_cs address valid up_ad[11:0] up_r/w data valid up_d[15:0] t acc t ch t ws up_oe t ah t li
mt90222/3/4 data sheet 141 zarlink semiconductor inc. note 1 - for internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid ac cess. figure 33 - cpu interface mo torola timing - write access ac electrical characteristics - cpu interface motorola timing - write cycle characteristics sym. min. typ. max. units test conditions 1up_r/w set-up time to up_cs falling edge t ws 1ns 2 address and data set up before rising edge of up_cs t su 10 ns 3 up_ad and data hold time after up_cs rising edge t adh 4ns 4up_r/w low after rising edge or up_cs t wh 1ns 5up_cs high before next up_cs low t csh 2 (see note 1) cycle system clock up_cs address valid up_ad[11:0] up_r/w data valid up_d[15:0] t su t ws up_oe t adh t csh t wh
mt90222/3/4 data sheet 142 zarlink semiconductor inc. note 1 - for internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid ac cess. figure 34 - cpu interface intel timing - write access ac electrical characteristi cs - cpu interface intel timing - write cycle characteristics sym. min. typ. max. units test conditions 1up_cs set-up time to up_r/w falling edge t ws 1ns 2 address and data set up before rising edge of up_r/w t su 10 ns 3 up_ad, up_cs and data hold time after up_r/w rising edge t adh 4ns 4up_r/w low after rising edge or up_cs t csh 1ns 5up_cs high before next up_cs low t wh 2 (see note 1) cycle system clock up_cs address valid up_a[11:0] up_r/w data valid up_d[15:0] t su t ws up_oe t adh t wh (read) (write) t csh
mt90222/3/4 data sheet 143 zarlink semiconductor inc. ac electrical characteristics - serial streams frame pulse and clk characteristic sym. min. typ. max. units notes 1 frame pulse width (st-bus, generic) bit rate = 2.048 mb/s bit rate = 4.096 mb/s bit rate = 8.192 mb/s t fpw 26 26 26 ns ns ns max width is one clock period. 2 frame pulse setup time (st-bus or generic) t fps 5ns 3 frame pulse hold time (st-bus or generic) t fph 10 ns 4 frame pulse output delay t fod 25 ns c l =150 pf 5clk period bit rate = 2.048 mb/s bit rate = 4.096 mb/s bit rate = 8.192 mb/s t cp 190 110 55 300 150 70 ns ns ns 6 clk pulse width high bit rate = 2.048 mb/s bit rate = 4.096 mb/s bit rate = 8.192 mb/s t ch 85 50 20 150 75 40 ns ns ns 7 clk pulse width low bit rate = 2.048 mb/s bit rate = 4.096 mb/s bit rate = 8.192 mb/s t cl 85 50 20 150 75 40 ns ns ns 8 clock rise/fall time t r , t f 10 ns ac electrical characteristics - serial streams for st-bus and generic interface characteristic sym. min. typ. m ax. units test conditions 1 sti set-up time t sis 5ns 2sti hold time t sih 10 ns 3 sto delay - active to active t sod 25 ns c l =150 pf 4 sto delay - active to high-z t dz 25 c l =150 pf 5 sto delay - high-z to active t zd 25 c l =150 pf 6 output driver enable (ode) delay t ode 25 ns c l =150 pf
mt90222/3/4 data sheet 144 zarlink semiconductor inc. figure 35 - st-bus timing v ct v ct f0i clk t fpw sto sti t fph t sod t sih t ch t cl bit 0, last ch (note1) 2.048 mb/s mode, last channel = ch 31, 4.196 mb/s mode, last channel = ch 63, 8.192 mb/s mode, last channel = ch 127. t fps t cp t sis v ct v ct bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 bit 0, last ch (note1) bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 note 1: v ih(min) v il(max) t r t f f0o v ct t fod
mt90222/3/4 data sheet 145 zarlink semiconductor inc. figure 36 - generic bus timing 2 mb/s mode, last channel = ch 31, 4 mb/s mode, last channel = ch 63, 8 mb/s mode, last channel = ch 127 note 1: v ct v ct f0i clk t fpw sto sti t fph t sod t sih t ch t cl bit 0, last ch (note1) t fps t cp t sis v ct bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 bit 0, last ch (note1) bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 t r t f (positive) f0i (negative) (positive) clk (negative) f0o (positive) f0o (negative) t fod v ct v ih(min) v il(max) v ct
mt90222/3/4 data sheet 146 zarlink semiconductor inc. note ? : typical figures are at 25 c, v dd =3.3 v, and for design aid only: not guaranteed and not subject to production testing. figure 37 - tdm ring tx timing diagram figure 38 - tdm ring rx timing diagram ac electrical characteristics ? - tdm ring bus characteristic sym. min. typ. ? max. units test conditions 1 txringclk/rxringclk period t rtxp /t rrxp 19 20 20 ns must be synchronous with the system clock 2 txringclk/rxringclk period high t rtxh /t rrxh 10 ns 2 txringclk/rxringclk period low t rtxl /t rrxl 10 ns 3 txringsync/txringdata output delay t rtxod 04ns 5 rxringsync/rxringdata setup time t rrxs 2ns 6 rxringsync/rxringdata hold time t rrxh 2ns txringsync t rtxh txringclk txringdata [7:0] t rtxod t rtxl t rtxp rxringsync t rrxh rxringclk rxringdata [7:0] t rrxh t rrxl t rrxp t rrxs
mt90222/3/4 data sheet 147 zarlink semiconductor inc. note ? : typical figures are at 25 c, v dd =3.3 v, and for design aid only: not guaranteed and not subject to production testing. figure 39 - jtag port timing ac electrical character istics - jtag port and reset pin timing parameter symbol min. typ. ? max. units test conditions tck period width t tclk 100 ns bsdl spec?s 12 mhz tck period width low t tclkl 40 ns tck period width high t tclkh 40 ns tdi setup time to tck rising t disu 2ns tdi hold time after tck rising t dih 33 ns tms setup time to tck rising t mssu 2ns tms hold time after tck rising t msh 5ns tdo delay from tck falling t dod 20 ns c l = 30 pf trst pulse width t trst 15 ns reset pulse width t rst 2 ms 70 mclk cycles t mssu tdi tdo tms tck t disu t msh t dih t dod t tclkh t tclkl t tclk trst t trst
mt90222/3/4 data sheet 148 zarlink semiconductor inc. note ? : typical figures are at 25 c, v dd =3.3 v, and for design aid only: not guaranteed and not subject to production testing figure 40 - system clock and reset ac electrical characteristics - system clock and reset parameter symbol min. typ. ? max. units test conditions clk period width 1 1. the system clock period cannot be longer than the tx or rx utopia clock period. t clk 19 20 20 ns for full operation of tdm ring, otherwise could be longer clk period width low t clkl 8.5 10 ns the min clk period width restrictions still need to be maintained clk period width high t clkh 8.5 10 ns the minimum time is measured at 1.4v clk rising t clkr 6 ns between 10%-90% of voltage levels clk falling t clkf 6 ns between 10%-90% of voltage levels reset pulse width t rst 10 clk period reset t rst clk t clkh t clkl t clk t clkr t clkf
mt90222/3/4 data sheet 149 zarlink semiconductor inc. 10.0 list of abbreviations and acronyms aal atm adaptation layer atm asynchronous transfer mode cbr constant bit rate cdv cell delay variation cpe customer premises equipment crc cyclic redundancy check ctc common transmit clock dsu data service unit fe far end gsm group state machine gtsm group transmit state machine hec header error control idcr ima data cell rate i/f interface ifsm ima frame state machine ima inverse multiplexing for atm isdn integrated services digital network itc independent transmit clock lcd loss of cell delineation lid link identification lif loss of ima frame lods link out of delay synchronization lof loss of frame los loss of signal lsm link state machines m ima frame size mib management information base mvip multi-vendor integration protocol ne near end oam operations, administration and maintenance ocd out of cell delineation (anomaly) oif out of ima frame (anomaly) pdh plesiochronous digital hierarchy phy physical layer pmd physical medium dependent
mt90222/3/4 data sheet 150 zarlink semiconductor inc. qos quality of service rai remote alarm indication rdi remote defect indication rfi remote failure indication sar segmentation and reassembly scci status and control change indication soc start of cell tc transmission convergence trl timing reference link trlcr timing reference link cell rate utopia universal test and operations physical interface for atm uni user network interface 11.0 atm glossary asynchronous transfer mode adaptation layer (aal) - standardized protocols used to translate higher layer services from multiple applications into the size and fo rmat of an atm cell. individual protocols are indexed as per the examples below: aal0 - native atm cell transmission proprietary protoc ol featuring 5-byte header and 48-byte user pay- load. aal1 - used for the transport of constant bit rate, time -dependent traffic (e.g., voice, video); requires trans- fer of timing information between source and destinati on; maximum of 47-bytes of user data permitted in payload as an additional header byte is required to provide sequencing information. aal5 - usually used for the transport of variable bit rate, de lay-tolerant data traffic and signalling which requires little sequencing or error-detection support. active - this is a link state indicating the link is capab le of passing atm layer cells in the specified direction. aligned - ima frames are said to be aligned if they are transmitted simultaneously. asynchronous 1. not synchronous; not periodic. 2. the temporal property of being sourced from independ ent timing references, having different frequencies and no fixed phase relationship 3. in telecommunications, data which is not synchronized to the public network clock. 4. the condition or state of being unable to determine exac tly when an event will trans pire prior to its occurrence. asynchronous transfer mode (atm ) - a method of organizing information to be transferred into fixed-length cells; asynchronous in the sense that the recurrence of cells cont aining information from an individual user is not neces- sarily periodic. note: although atm cells are transmitted synchronously to maintain the clock between sender and receiver, the sender transmits data cells on an as available basis and transmits empty cells when idle. the sender is not limited to transmitting data every nth ce ll. blocked - the blocked state is a group state indi cating that the group has been inhibited. blocking - blocking is a transitional state that allows grac eful transition into the unusable state without loss of atm layer cells.
mt90222/3/4 data sheet 151 zarlink semiconductor inc. cell - fixed-size information package consisting of 53 byte s (octets) of data; of thes e, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead. cell delay variation (cdv ) - a qos parameter that measures the peak-t o-peak cell delay through the network; re- sults from buffering and cell scheduling. common transmit clock (ctc) configuration - this is a configuration where t he transmit clocks of all links within the ima group are derived fr om the same clock source. constant bit rate - an atm service category supporting a constant or guaranteed rate, with timing control and strict performance parameters. used for services such as voice, video, or circuit emulation. filler cell - a filler cell is used to fill in the ima frame when no cells are available at the atm layer. it is used for performing cell rate decoupling at the im a sublayer (e.g., similar to the idle cell used in single link interfaces). header error control (hec) - atm equipment (usually the phy) uses the fifth octet in the atm cell header to check for an error and correct the contents of the header; crc al gorithm allows for single-erro r correction and multiple-er- ror detection. i.363 - itu-t recommendation specifying the aals for b-isdn. ima frame - the ima frame is used as the unit of control in the ima protocol. it is defined as m consecutive cells, on each of n links, where 1 n 32 (determined by the um and ima link start-up procedure), in an ima group. one of the m cells on each of the n links is an icp cell that oc curs within the frame at the icp cell offset position. this offset position may be different between links. the ima frame is aligned on all links. differential link delay can cause the reception to be ?mis-aligned? in time. alignment can be recovered using a link delay synchronization mechanism. the icp ?stuff? mechanism is a controlled viol ation of the ima consecutive frame definition. ima group - the ima group is a ?group? of links at one end of a ?circuit? that establish an ima virtual link to another end. ima sublayer - the ima sublayer is part of the physical layer that is located between the interface specific trans- mission convergence sublayer and the atm layer. ima virtual link - the ima virtual link is a virt ual circuit established between two ima ends over a number of phys- ical links (i.e., ima group). inhibiting - inhibiting is a voluntary action th at disables the capacity of a group or link to carry atm layer cells for reasons other than reported problems. insufficient links - this is a group state indicating that the group does not have sufficient links to be in the oper- ational state. independent transmit clock (itc) configuration - this is a configuration where the transmit clock of at least one link within the ima group is not derived from a common clock source. isochronous - the temporal property of an event or signal re curring at known periodic time intervals (e.g., 125 s). isochronous signals are dependent on some uniform timing, or carry their own timing information embedded as part of the signal. examples are ds-1/t 1 and e1. from the root words, ?iso? meaning equal, and ?chronous? meaning time. itu-t - international telecommunications union telecommunications standards sector. layer management functions - the layer management functions relate to processing of actions such as config- uration, fault monitori ng and performance moni toring within the group.
mt90222/3/4 data sheet 152 zarlink semiconductor inc. loss of cell delineation (lcd) - the lcd defect is reported when the ocd anomaly persists for the period of time specified in itu-t recommendation i.432(30)?. the l cd defect is cleared when the ocd anomaly has not been detected for the period of time specified in itu-t recommendation i.432. lcd remote failure indication (lcd-rfi) - the lcd-rfi is reported to the fe when a link defect is locally detect- ed. the lcd-rfi defect is not al ways required on the link interface. link delay synchronization (lds) - the lds is an event indicating that the link is synchronized with the other links within the ima group with respect to differential delay. loss of ima frame (lif) defect - the lif defect is the occurrence of persistent oif anomalies for at least gamma + 2 ima frames. link out of delay (lods) synchronization defect - the lods is a link event indica ting that the link is not syn- chronized with the other links within the ima group. multi-vendor integration protocol (mvip) - mvip standards are designed to supp ort the inter-operability of prod- ucts from different manufacturers and the portability of computer software between pr oducts from diff erent manufac- turers with the goal of facilitating new and improved applications of computer and communications equipment. out of cell delineation (ocd) anomaly - as specified in itu-t recommendation i.432(30), an ocd anomaly is reported when alpha consecutive cells wi th incorrect hec are received. it c eases to be reported when delta con- secutive cells with correct hec are received. out of ima frame (oif) anomaly - the oif is the occurrence of an ima anomaly as defined in the inverse multi- plexing for atm specification. operational - the operational state is a group state that has sufficient links in both the transmit and receive direc- tions to carry atm layer cells. plesiochronous - the temporal property of being arbitrarily clos e in frequency to some defined precision. plesio- chronous signals occur at nominally the same rate, any variat ion in rate being constrained within specific limits. since they are not identical, over the long term they will be skewed from each other. this will force a switch to occasionally repeat or delete data in order to handle buffer under-flow or overflow. (in tele communications, this is known as a frame slip). physical layer (phy) - bottom layer of the atm reference model; provides atm cell transmission over the physical interfaces that interconnect the various atm devices. quality of service (qos) - atm performance parameters that characterize the transmi ssion quality over a given vc (e.g cell delay variation; cell transfer delay, cell loss ratio). stuff event - the stuff event is the repetition of an icp cell over one ima li nk to compensate for a timing difference with other links within the ima group. synchronous 1. the temporal property of being sourced from the same timing reference. synchron ous signals have the same frequency, and a fixed (often implied to be zero) phase offset. 2. a mode of transmission in which the sending and receivi ng terminal equipment are operating continually at the same rate and are maintained in a desired phase relationship by an appropriate means. universal test and operations ph ysical interface for atm (utopia) - a phy-level interface to provide connec- tivity between atm components. unusable - the unusable state is a link state indicating that a link is not in use due to a fault, inhibition, etc.
mt90222/3/4 data sheet 153 zarlink semiconductor inc. usable - the usable state is a link state i ndicating the link is ready to operate in the specified direction, but is waiting to move to the action state. virtual channel (vc) - one of several logical connections defined within a virtual path (vp) between two atm de- vices; provides sequential, unidirectional transport of atm cells. also virtual circuit . glossary references: the atm glossary - atm year 97 - version 2.1, march 1997 the atm forum glossary - may 1997 atm and networking glossary (http://www.techguide. com/comm/index.html) zarlink semiconductor glossary of telecommunications terms - may 1995.
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